Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-06
2003-03-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06539525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly, to a method of verifying the layout of an integrated circuit device including a memory block and a logic block.
2. Description of the Related Art
Generally, application specific integrated circuit (ASIC) products are designed using the following five steps: 1) system option determination; 2) schematic circuit design of a circuit which performs a related function; 3) circuit verification; 4) placing/routing and layout verification; and 5) mask fabrication.
In the placing/routing of step 4), circuit elements on a net list, which is extracted in the schematic circuit design step, are realized as a layout of geometrical polygons and interconnections. In the layout verification of step 4), a net list is extracted from the layout expressed with polygons and interconnections, in contrast to the layout generation, and the extracted net list is compared to the original net list.
In the ASIC design industry, designs or layouts of functional blocks that are repeatedly used in integrated circuits are often copyrighted and commercialized. A vendor can then provide the functional block designs to other companies, and products can be manufactured using the designs and process of the vendor. Generally in these situations, the input and output characteristics, operation model, etc. of the functional blocks are provided to facilitate product design. The company using the functional block design processes an area containing the functional block, as a black box that includes only input and output terminals and does not include internal circuits. The company then performs the above designing step of placing/routing and layout verification. Finally, the mask information of the purchased design is inserted into the black box upon the manufacture of a mask. The use of a black box prevents circuit-level information from leaking to other companies and protects the vendor's technology.
In the placing/routing process of ASIC design including a black box, the interconnections between functional blocks are drawn to be connected up to the input and output terminals of the black boxes, since the black box includes no circuits for laying-out, as described above. At this time, a specific character is positioned at the ends of the interconnection shown up to the input and output terminals to help verify the layout later.
The verification of the layout is performed with respect to all areas except for the black box areas. At this time, it is impossible to check whether the layout has been shown such that the input and output terminals of the black box are properly connected to the interconnection. Merely indirect verification is made by checking the specific character at the ends of the interconnection which is connected to the input and output terminals.
Hence, even if computers analyze a layout and determine that there are no errors in the layout, it cannot be determined whether the layout of the input and output terminals of the black box and the interconnection have been properly drawn. At present, the connections to the input and output terminals of the black box are checked with the naked human eye after layout verification. This visual inspection may increase the designing time. Even with an entire circuit corresponding to the black box, when the circuit of the black box is as large as a memory core, verifying a layout can take a considerable amount of time. Furthermore, this visual inspection may generate errors. These drawing errors cause inferior products, for example, by failing to electrically connect a memory core portion to the input and output terminals of a product.
For these reasons, what is needed is an efficient and quick method for accurately generating and verifying an integrated circuit device layout having a black box area.
SUMMARY OF THE INVENTION
One aspect of the present invention is to provide a method of verifying the layout of an integrated circuit device, by which electrical disconnection between a plurality of ports and a memory core area can be accurately detected upon verification of a circuit to the layout. In this aspect of the present invention, a method is provided for generating and verifying the layout of an integrated circuit device having a black box area. The method includes: inserting a dummy circuit into the black box area; simultaneously placing and routing the integrated circuit device including the black box area, using a computer; and automatically verifying the connection between the input and output terminals of the back box area and a routing metal when the integrated circuit device is subjected to circuit-to-layout verification by a computer.
Preferably, a memory core is disposed in the black box area, and the dummy circuit is a logic gate tree circuit having a plurality of logic gates. The dummy circuit is preferably designed before the dummy circuit is first applied to the black box area and placed and routed.
In accordance with another aspect of the present invention, a method of verifying the layout of an integrated circuit device prevents metal traces from penetrating into a memory core region upon placing and routing. The method includes: arranging a plurality of blockages one by one between adjacent input and output ports in the memory block; simultaneously placing and routing the integrated circuit device using a computer; and performing a design rule check on the integrated circuit device which has been placed and routed using a computer.
Preferably, each of the blockages is between two adjacent input and output ports which have a wide interval therebetween. Verification of a circuit layout is performed after placing and routing the integrated circuit device. Also, the blockages are preferably made of metal and are processed as additional cells and skipped upon the manufacture of a final pattern generator.
In a third aspect of the present invention, a method accurately generates and verifies the layout of an integrated circuit device having a memory block by using a dummy circuit. The method includes: inserting a dummy circuit into the memory block and arranging a plurality of blockages one by one between adjacent input and output ports in the memory block; simultaneously placing and routing the integrated circuit device, using a computer; and performing a design rule check and a circuit-to-layout verification with respect to the integrated circuit device which has been placed and routed, using a computer.
These and other features and advantages of the present invention will be more readily apparent from the detailed description of the embodiments set forth below taken in conjunction with the accompanying drawings.
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Harness Dickey & Pierce PLC
Lin Sun James
Samsung Electronics Co,. Ltd.
Siek Vuthe
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