Layout to minimize gate orientation related skew effects

Details Layout to minimize gate orientation related skew effects Layout to minimize gate orientation related skew effects

2005-05-17

2005-05-17

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S213000

Reexamination Certificate

active

06893925

ABSTRACT:
A method and apparatus for a driver layout is described. The layout includes an first number of gate lines arranged along a first axis and a second equal number of gates arranged along a second axis, such that the first set of gates lines is orthogonal to the second set of gates lines. The layout includes a total of N discrete transistors.

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Mathias et al., “Flag: A flexible layout generator for analog MOS transistors”, Jun. 6, 1998, Solid-State Circuits, IEEE Journal, vol. 33 Issue, pp.: 896-903.

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