Layout schemes and methods of power gating transistor...

Details Layout schemes and methods of power gating transistor... Layout schemes and methods of power gating transistor...

2007-06-20

2010-11-23

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07840926

ABSTRACT:
A semiconductor device may include a logic circuit and one or more power gating transistor switches. The logic circuit may be connected between a power voltage and a ground voltage, and may perform one or more logic operations. The one or more power gating transistor switches may include a plurality of power gating transistors and poly resistors, and may switch application of the power voltage to the logic circuit according to an active mode, a sleep mode, or active and sleep modes of the logic circuit. The one or more power gating transistor switches may use the poly resistors to sequentially apply the power voltage to the logic circuit, to sequentially block the application of the power voltage to the logic circuit, or to sequentially apply the power voltage to the logic circuit and to sequentially block the application of the power voltage to the logic circuit.

REFERENCES:
patent: 6492689 (2002-12-01), Yamauchi et al.
patent: 6800497 (2004-10-01), Wang et al.
patent: 6876252 (2005-04-01), Kim et al.
patent: 2004/0222817 (2004-11-01), Madurawe
patent: 2005/0091630 (2005-04-01), Madurawe
patent: 2005/0270074 (2005-12-01), Hardee
patent: 2006/0069937 (2006-03-01), Peng

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