Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Utility Patent
1999-07-01
2001-01-02
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000
Utility Patent
active
06169314
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits.
(2) Description of the Related Art ESCRIPTION OF THE RELATED ART
Matched pairs of transistors are important in precision analog circuits. There are conventional layout methods to design matched pairs in integrated circuit elements, such as cross-coupled metal oxide semiconductor field effect transistor layouts. These methods use a relatively large area of the integrated circuit element and do not handle short channel lengths of about 1.0 micrometer or less effectively.
The layout methods of this invention use a smaller area of the integrated circuit element and produce good matching results at channel lengths as low as 0.8 micrometers.
SUMMARY OF THE DISCLOSURE
Matching the parameters of metal oxide field effect transistors, or MOSFETs, is very important when the MOSFETs are used in critical analog circuits.
FIG. 1
shows a conventional cross-coupled layout of four P channel metal oxide semiconductor field effect transistors, or PMOSFETs, in an integrated circuit element. The first, second, third, and fourth PMOSFETs are laid out in a rectangle as shown in FIG.
1
. The first PMOSFET has a first channel diffusion area
100
, a first gate electrode
103
, and a first drain electrode
101
, and a first source electrode
102
. The second PMOSFET has a second channel diffusion area
110
, a second gate electrode
113
, and a second drain electrode
111
, and a second source electrode
112
. The third PMOSFET has a third channel diffusion area
120
, a third gate electrode
123
, and a third drain electrode
121
, and a third source electrode
122
. The fourth PMOSFET has a fourth channel diffusion area
130
, a fourth gate electrode
133
, and a fourth drain electrode
131
, and a fourth source electrode
132
. The first
100
, second
110
, third
120
, and fourth
130
channel diffusion areas are rectangular each rectangle having two long sides and two short sides.
As shown in
FIG. 1
the PMOSFETs are in a 2×2 array with the first PMOSFET and second PMOSFET in the first row, the third PMOSFET and fourth PMOSFET in the second row, the first PMOSFET and third PMOSFET in the first column, and the second PMOSFET and fourth PMOSFET in the second column. The long sides of the channel diffusion areas
100
,
110
,
120
, and
130
lie on four parallel lines. The short sides of the channel diffusion areas
100
,
110
,
120
, and
130
lie on four parallel lines which are perpendicular to the lines containing the long sides.
FIG. 2
shows the sources of the four PMOSFETs connected together at a source node
17
for test purposes. The first PMOSFET
10
and the fourth PMOSFET
13
form a first transistor in the matched pair, and the second PMOSFET
11
and third PMOSFET
12
form a second transistor in the matched pair in the cross-coupled arrangement.
FIG. 3
shows the mismatching test results as a function of PMOSFET size, for channel widths between about 0.8 micrometers and 20 micrometers and channel lengths between about 0.65 micrometers and 4.0 micrometers, for cross-coupled PMOSFET arrays as described above and shown in
FIGS. 1 and 2
. The curves in
FIG. 3
show the mean difference in threshold voltage
36
in millivolts, the standard deviation of the difference in threshold voltage
31
, the mean difference of drain current factor
34
in percent, the standard deviation of the difference of drain current factor
35
, the mean difference in drain current
33
in percent, and the standard deviation of the difference in drain current
32
all as a function of PMOSFET size. Drain current factor, B, is defined by the equation I
d
=&bgr;(V
g
−V
t
)
60
; where I
d
is the drain current, V
g
is the gate voltage, V
t
is the threshold voltage, and &agr; is the velocity factor. The PMOSFET sizes are for a channel width of about 20 micrometers with channel lengths of 0.65, 0.9, 1.1, 1.6, 2.0, and 4.0 micrometers; a channel width of 1.6 micrometers with channel lengths of 0.65, 0.9, 1.1, and 1.6 micrometers; a channel width of 1.2 micrometers with a channel length of 0.9 micrometers; and a channel width of 0.8 micrometers with a channel length of 0.9 micrometers. As can be seen in
FIG. 3
the mismatching increases as the channel width or channel length decreases.
It is a principle objective of this invention to provide a circuit layout of metal oxide semiconductor field effect transistors, or MOSFETs, which will provide improved matching of matched pairs of transistors used in analog circuits and extend to lower channel widths or channel lengths.
It is another principle objective of this invention to provide a method of matching of metal oxide semiconductor field effect transistors, or MOSFETS, for use as matched pairs in analog circuits and extend to lower channel widths or channel lengths.
These objectives are accomplished by using a circuit layout of MOSFETs which places a number of MOSFETs in a row in an integrated circuit element, such as that shown in FIG.
4
. In this type of circuit layout there is a dummy MOSFET on either side of each MOSFET which is part of a matched pair of MOSFETs. The MOSFETs of the matched pair are adjacent to each other in the row.
FIG. 4
shows a first MOSFET
401
, a second MOSFET
402
, a third MOSFET
403
, and a fourth MOSFET
404
arranged in a row such that a line representing the direction of source to drain current flow of each MOSFET is parallel to the line representing the direction of source to drain current flow of the other transistors in the row. The dummy MOSFET can be a part of the matched pair, can be used for other purposes, or need not be used. The presence of the dummy MOSFETs on either side of each MOSFET in the matched pair provides significant improvement of the matching characteristics of the matched pair.
As an example refer to FIG.
4
. If the second MOSFET
402
and the third MOSFET
403
make up the matched pair, the first MOSFET
401
and the third MOSFET
403
serve as the dummy MOSFETs for the second MOSFET
402
, and the second MOSFET
402
and the fourth MOSFET
404
serve as the dummy MOSFETs for the third MOSFET
403
. The second MOSFET
402
serves as a dummy MOSFET for the third MOSFET
403
even though it is part of the matched pair of MOSFETs.
REFERENCES:
patent: 5610429 (1997-03-01), Crafts
patent: 5877537 (1999-03-01), Aoki
patent: 5952698 (1999-09-01), Wong et al.
patent: 6066866 (2000-05-01), Omori
patent: 6066870 (1999-09-01), Siek
patent: 6084794 (2000-07-01), Lu et al.
“The Design of High-Performance Analog Circuits On Digital CMOS Chips” by E.A. Vittoz in IEEE Journal of Solid State Circuits, vol. SC-20, No. 3, Dec. '85, pp. 3-11.
“Measurement of MOS Current Mismatch in the Weak Inversion Region” vol. 29 No. 2, Feb. 1994, pp.138-142.
Ting Jyh-Kang
Tseng Pin-Nan
Wong Shyh-Chyi
Ackerman Stephen B.
Clark Sheila V.
Prescott Larry J.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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