Layout of semiconductor memory device and method of...

Details Layout of semiconductor memory device and method of... Layout of semiconductor memory device and method of...

2005-12-06

2008-11-25

Tran, Minh-Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27084, C257SE27085, C257SE25023, C365S145000, C365S149000, C365S185200, C365S210100

Reexamination Certificate

active

07456457

ABSTRACT:
Provided are a layout of a semiconductor memory device capable of minimizing an occupation area of a dummy cell array and a method of controlling capacitance of a dummy cell to be same with that of the memory cell. The layout includes a dummy cell connected to one side of a sense amplifier, in which the dummy cell has a capacitance identical to a capacitance of the memory cell. The dummy cell is connected to one side of a sense amplifier connected to the memory cell and arranged in a column direction of the semiconductor substrate.

REFERENCES:
patent: 5682343 (1997-10-01), Tomishima et al.
patent: 6333870 (2001-12-01), Kang
patent: 6751152 (2004-06-01), Hsu et al.
patent: 2004/0085844 (2004-05-01), Arimoto et al.
patent: 1991-8925 (1991-10-01), None
patent: 1997-0008176 (1997-02-01), None
patent: 1999-23425 (1999-03-01), None
English language abstract of Korean Publication No. 1997-0008176.
English language abstract of Korean Publication No. 1991-8925.
English language abstract of Korean Publication No. 1999-23425.

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