Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-20
2004-05-04
Elms, Richard (Department: 2815)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06732345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout and wiring system and a wiring method for use in the automatic layout and wiring system, and more particularly, to a layout and wiring system and a wiring method for use in the automatic layout and wiring system, capable of wiring electronic components in accordance with a short-run rule which partially allows a wiring space smaller than the wiring minimum space according to a design rule only if a predetermined condition is fulfilled, and a recording medium which records the wiring method for use in the automatic layout and wiring system.
2 Description of the Related Art
In an LSI (Large-Scale Integration) layout design, art-work data regarding the wiring in the entire chip is created based on data regarding the wiring in a library. The creation of such art-work data is performed based on the chip size and a circuitry diagram which are shown in the unit of logical functions (blocks) a collection of which are prepared as a library. The creation of such art-work data is performed using an automatic layout and wiring system as a CAD (Computer Aided Design) system. Along with the large scale and rapid development in the integration of the LSI chips in recent years, a higher degree of integration in automatic layout and wiring systems is desired. Hence, it is demanded that automatic layout and wiring systems include a wiring function for wiring a number of wiring layers and be able to wire electronic components even if a number of vias for connecting the wiring layers are included.
The structure of the conventionally-used automatic layout system and a process for automatically layout and wiring electronic components will now schematically be explained.
FIG. 11
is a diagram showing the structure of the automatic layout and wiring system. In the automatic layout and wiring system
1
, reading/previous processing means
6
is prepared for: (1) reading information regarding the connection made between terminals of each block forming an LSI to be designed from a circuitry diagram information file
2
; (2) reading ad-work data regarding cells/blocks for use in the LSI to be designed, from information regarding vias or cells such as a NAND gate, etc. and registered in a cell/block library
3
, and/or information including any blocks for realizing complicated logical functions; (3) and reading, from a design rule file
4
, a design rule for wiring electronic components under some conditions, such as a wiring pitch between wiring layers, the wiring width, the wiring minimum space, and the size of each element forming a via cell, and for inspecting the above conditions. On the basis of the read information, main automatic layout and wiring means
7
creates data for laying out and wiring the cells/blocks, and carries out the process for laying out and wiring the cells/blocks. Resultant layout and wiring inspection means
8
inspects the resultant layout and wiring performed by the main automatic layout and wiring means
7
. If there is no defect in the resultant wiring which has undergone the inspection, the data regarding the resultant wiring is re-converted into art-work data. Thereafter, the art-work data is output from the automatic layout and wiring system
1
to a layout and wiring result output file
5
. On the contrary, if a defect is found during the inspection, the defect is corrected, and the process for laying out and wiring the cells/blocks is carried out again, by inputting/editing means (not illustrated) which is included in the automatic layout and wiring system
1
.
FIG. 12
is a flow diagram for explaining the entire process for laying out and wiring electronic components. In a process
121
for reading a library, the automatic layout and wiring system reads out circuitry information, the wiring pitch, the wiring width, the wiring minimum space, the side length of each via, and information regarding blocks to be arrayed. Such information are registered in advance as library data in the circuitry diagram information file
2
, the cell/block library
3
, the design rule file
4
. Further, the automatic layout and wiring system sets a rule for laying out and wiring the electronic components. In a process
122
for laying out cells/blocks, the primitive cells and the logical functional blocks, which are illustrated in the circuitry diagram, are automatically laid out in an LSI chip. In a process
123
, for wiring cells/blocks, terminals between cells/blocks are automatically wired in accordance with a set rule. In a process
124
, for inspecting wired cells/blocks, the electronic components are inspected as to whether there is an un-laid block, any unconnected portion of wiring, and whether there is a shorted circuit. In a process
125
for outputting data regarding the laid out and wired cells/blocks, data for the automatic layout and wiring system is converted into art-work data corresponding each wiring pattern forming an LSI, and the converted data is output to the layout and wiring result output file
5
. Then, the entire process for laying out and wiring the electronic components is completed.
FIG. 13
is a flow diagram for specifically explaining the process
121
, which is included in the entire process for laying out and wiring electronic components shown in FIG.
12
. The conventional process
121
includes a process
131
, for reading out circuitry diagram information from the circuitry diagram information file
2
and writing the read information into the automatic layout and wiring system, a process
132
, for reading design rule information from the design rule file
14
, and a process
133
for reading information regarding any cells/blocks for use in laying out and wiring the electronic components from the cell/stock library
3
.
The process
132
, includes steps
134
,
135
,
136
,
137
and
138
. The step
134
is prepared for reading a wiring pitch P indicating a space between grid lines in the wiring. The step
135
is prepared for reading a wiring width W which is a standard level for signal wiring. The step
136
is prepared for reading the wiring minimum space S which is the allowable minimum value for a space between a portion of wiring and another portion of wiring. The step
137
is prepared for reading a side length V of a via in a via cell. The step
138
is prepared for reading a via margin M.
FIG. 14A
is a planer view of a via cell, and
FIG. 14B
is a cross sectional view exemplarily showing a via cell included in an LSI. In a via cell
23
shown in
FIG. 14A
, a via
141
for connecting upper wiring with lower wiring is formed in a square shape having a side length V. As shown in
FIG. 14B
, a lower wiring layer
22
a
and an upper wiring layer
21
a
are larger in width than the wire by via margins M, which is prepared on all sides of the via
141
, than the via
141
. In this structure, the via
141
does not extend beyond the upper wiring layer
21
and the lower wiring layer
22
a
, even if the positional deviation occurs between the via and the lower wiring layer pattern and/or between the via and the upper wiring layer pattern in a lithography process during the LSI manufacture. A reference numeral
142
denotes an insulation layer such as a silicon oxide film, etc.
As shown in
FIG. 13
, the process
133
includes a step
139
of reading an art-work cell name of the via cell
23
, and a step
140
of reading information regarding any cells/blocks for use in laying out and wiring the electronic components.
FIGS. 15A and 15B
are diagrams each exemplarily showing output art-work data of wiring according to a conventional wiring method. As shown in the first conventional wiring method of
FIG. 15A
, based on its design rule, there are several conditions that a wiring pitch P=1.00 &mgr;m, a wiring width W=0.50 &mgr;m, the wiring minimum space S=0.50 &mgr;m, a side length of each via V=0.50 &mgr;m, and a via margin M=0.05 &mgr;m. The wiring space between portions of wiring, extending along grid lines which ar
Chu Chris C
Elms Richard
Foley & Lardner
NEC Electronics Corporation
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