Layout generation and optimization to improve...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

11193133

ABSTRACT:
Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.

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patent: 2000243694 (2000-09-01), None
Haruki, Tamae, et al., “MASCOT: Mask Pattern Correction Tool Using Genetic Algorithm”, Japanese Journal of Applied Physics, vol. 35, Dec. 1996, pp. 6374-6378.
Rosenbluth, Alan E. et al., “Optimum Mask and Source Patterns to Print a Given Shape”, Journal of Microlithography, Microfabrication, and Microsystems, vol. 1, Apr. 2002, pp. 13-30.

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