Layout for noise reduction on a reference voltage

Details Layout for noise reduction on a reference voltage Layout for noise reduction on a reference voltage

1994-07-05

1997-09-23

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257665, 257776, H01L 2976, H01L 31062

Patent

active

056708157

ABSTRACT:
A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.

REFERENCES:
patent: 4905068 (1990-02-01), Satoh et al.
patent: 4937649 (1990-06-01), Shiba et al.
patent: 4941031 (1990-07-01), Kumagai et al.
patent: 5006918 (1991-04-01), Deutsch et al.
patent: 5014110 (1991-05-01), Satoh
patent: 5027174 (1991-06-01), Mimoto
patent: 5208725 (1993-05-01), Akcasu
patent: 5446311 (1995-08-01), Ewen et al.
patent: 5471093 (1995-11-01), Cheung
"Motorola Communications Device Data", DL136/D, Rev 3, 1993, pp. 2-698 and 4-4. no month.

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