Layout for a semiconductor memory device having a triple well st

Details Layout for a semiconductor memory device having a triple well st Layout for a semiconductor memory device having a triple well st

1998-11-04

1999-11-02

Dinh, Son T.

Static information storage and retrieval

Interconnection arrangements

365 51, 36518909, G11C 506

Patent

active

059782471

ABSTRACT:
A layout for a semiconductor memory device with a triple well structure, comprises a plurality of memory cell regions arranged in a matrix, a plurality of first circuit regions respectively arranged between adjacent ones of the memory cell regions along the first direction and each having the circuits to code and drive the word lines of corresponding memory cell region, a plurality of second circuit regions respectively arranged between adjacent ones of the memory cell regions in the second direction perpendicular to the first direction and each having the circuit to sense the bit line of corresponding bit line, a plurality of third circuit regions respectively arranged between adjacent ones of the first and second circuit regions, first drive elements applied with at least two well-bias voltages to drive the circuits of the first circuit regions, and second drive elements applied with another well-bias voltage to drive the circuit of the second circuit regions, wherein the first and second drive elements are respectively arranged in two adjacent ones of the third circuit regions.

REFERENCES:
patent: 5388084 (1995-02-01), Itoh et al.
patent: 5397734 (1995-03-01), Iguchi et al.
patent: 5650972 (1997-07-01), Tomishima et al.
patent: 5652726 (1997-07-01), Tsukude et al.
patent: 5822238 (1998-10-01), Okubo

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