Layout design and process to form nanotube cell for nanotube...

Details Layout design and process to form nanotube cell for nanotube... Layout design and process to form nanotube cell for nanotube...

2005-11-29

2005-11-29

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S690000, C365S151000

Reexamination Certificate

active

06969651

ABSTRACT:
Nanotube memory cells are formed on a semiconductor substrate. Lower and upper memory cell chambers are formed by forming a first trench overlying the first and second contacts in a nitride layer, forming a second trench overlying the first and second contacts in a dielectric layer, depositing a nitride layer on the combined lower and upper chambers, and patterning the nitride layer to form an access hole to the nanotube layer and a second access hole to the second contact. A conductive layer is then deposited and patterned to form a top electrode contact and a nanotube layer contact. The conductive material closes the aperture created by the access hole.

REFERENCES:
patent: 6643165 (2003-11-01), Segal et al.
patent: 6706402 (2004-03-01), Rueckes et al.
patent: 6734087 (2004-05-01), Hidaka et al.

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