Layered semiconductor wafer with low warp and bow, and...

Semiconductor device manufacturing: process – Chemical etching

Reexamination Certificate

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Reexamination Certificate

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07820549

ABSTRACT:
Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 6342725 (2002-01-01), Falster
patent: 6743495 (2004-06-01), Vasat et al.
patent: 2001/0007240 (2001-07-01), Dietze et al.
patent: 2003/0054641 (2003-03-01), Binns et al.
patent: 2003/0136961 (2003-07-01), Mule'Stagno et al.
patent: 2004/0023443 (2004-02-01), Kim et al.
patent: 2004/0142542 (2004-07-01), Murphy et al.
patent: 533 551 (1993-03-01), None
patent: 1 158 581 (2001-11-01), None
patent: 07-169925 (1995-04-01), None
patent: 09-326396 (1997-12-01), None
patent: 11-330437 (1999-11-01), None
patent: 2003-297839 (2003-10-01), None
patent: 2004-111732 (2004-08-01), None
patent: 98/52216 (1998-11-01), None
patent: 03/003430 (2003-01-01), None
A. Giannattasio, S. Senkader, S. Azam, R.J. Falster, P.R. Wilshaw: “The Use Of Numerical Simulation To Predict The Unlocking Stress Of Dislocations in CZ-silicon Wafers,” Microelectronic Engineering 70 (2003) pp. 125-130.
K. Jurkschat, S. Senkader, P.R. Wilshaw, D. Gambaro, R.J. Falster: “Onset Of Slip In Silicon Containing Oxide Precipitates,” J. Appl. Phys. vol. 90, No. 7 (2001), pp. 3219-3225.

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