Layer of high-k inter-poly dielectric

Details Layer of high-k inter-poly dielectric Layer of high-k inter-poly dielectric

2002-12-19

2004-06-22

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S630000, C438S954000

Reexamination Certificate

active

06753224

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a high-k inter-poly dielectric for the creation of small-scale gate electrodes.
(2) Description of the Prior Art
Gate electrodes, which form the essential component of flash memory devices, are typically created using overlying layers of semiconductor material, with the lowest layer being a layer of pad oxide (also referred to as a layer of gate dielectric) and the highest layer being a layer of silicided material that serves as a low resistivity electrical contact to the gate electrode. The layers of the gate electrode are typically overlying layers of dielectric, that can consist of polysilicon, separated by a layer of Inter-Poly Dielectric (ILD).
Current technology for the creation of gate electrodes uses a silicon dioxide layer as the gate dielectric for MOS devices. With a sharp reduction in device feature size, the thickness of the layer of gate dielectric must also be reduced, for the era of device features in the sub-micron range the gate thickness is approaching 2 nanometers or less. A continued reduction of the thickness of the layer of gate dielectric leads to increasing the tunneling current through this thin layer of gate dielectric. For this reason, a thin layer of silicon dioxide (thinner than about 105 nm) cannot be used as the gate dielectric for MOS devices having sub-micron device size.
The main issues facing the creation of ever smaller flash memories center on maintaining fast programming and erase time while simultaneously reducing the operating voltage of the device, frequently resulting in a trade-off between reduced power and high operating speed. The operating voltage must be reduced with reduced device dimensions, resulting in the requirement to increase the device-coupling ratio by increasing the floating gate capacitance of the device. This leads to the requirement of reducing the thickness of the layers of Inter Poly Dielectric (IPD) or to provide layers of IPD of advantageous dielectric properties. Among the most essential of these properties is the quality of the interface between the layers of dielectric that are selected to form the IPD. This because defects in interfaces between overlying layers of dielectric can cause a reduction in the signal to noise level of the device which, in sub-micron devices where a relatively small number of charges distinguishes between data bit states, quickly leads to an unacceptable design of the gate electrode.
Prior Art methods have primarily used silicon oxide as the material of choice for the creation of a layer of IPD, this in part because a layer of silicon oxide can be grown from an underlying layer of polysilicon. It has thereby long been recognized that grown layers of silicon oxide contain fewer defects (such as pinholes) than deposited layers of material.
From the above it is clear that efforts to reduce flash memory cell dimensions must focus not only on providing suitable materials for the creation of layers of IPD but must also provide methods whereby these layers of IPD can be properly deposited without causing interface defects. The invention addresses the first of these two aspects of creating flash memory cells by providing a novel high-k layer of Inter Poly Dielectric (IPD).
U.S. Pat. No. 5,923,056 (Lee et al.) shows an Al doped Zr dielectric layer.
U.S. Pat. No. 6,060,755 (Ma et al.) shows an Al doped Zr dielectric.
U.S. Pat. No. 6,008,091 (Gregor et al.) reveals a SiO
2
—TaO
5
—SiO
2
dielectric layer.
U.S. Pat. No. 6,171,910 (Hobbs et al.) and U.S. Pat. No. 6,020,243 (Wallace et al.) are related patents.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a high-k dielectric layer for use as an Inter Poly Dielectric (IPD) layer.
Another objective of the invention is to provide a gate dielectric that allows for reduced programming voltage of Electrically Erasable and Programmable Read Only Memory (EEPROM) devices.
Another objective of the invention is to provide a gate dielectric that allows for reduced programming time of Electrically Erasable and Programmable Read Only Memory (EEPROM) devices.
A still further objective of the invention is to provide a high-k dielectric layer for use as an Inter Poly Dielectric (IPD) layer of superior thermal stability.
In accordance with the objectives of the invention a new Inter Poly Dielectric (IPD) layer is provided for use in creating ultra-small gate electrodes. A first and a second high-k dielectric film are provided which remain amorphous at relatively high processing temperatures. The first high-k dielectric film is of Al
3
O
5
—ZrO
2
—Al
3
O
5
, the second high-k dielectric film is aluminum doped ZrO
2
or HfO
2
.


REFERENCES:
patent: 5298447 (1994-03-01), Hong
patent: 5923056 (1999-07-01), Lee et al.
patent: 6008091 (1999-12-01), Gregor et al.
patent: 6013558 (2000-01-01), Wallace et al.
patent: 6020243 (2000-02-01), Wallace et al.
patent: 6060755 (2000-05-01), Ma et al.
patent: 6153904 (2000-11-01), Yang
patent: 6171910 (2001-01-01), Hobbs et al.
patent: 6303454 (2001-10-01), Yeh et al.

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