Layer arrangement

Details Layer arrangement Layer arrangement

2005-08-01

2008-09-09

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S422000, C438S618000, C438S619000, C438S622000, C438S623000, C257SE21581

Reexamination Certificate

active

07422940

ABSTRACT:
A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.

REFERENCES:
patent: 5324683 (1994-06-01), Fitch et al.
patent: 6020261 (2000-02-01), Weisman
patent: 6661094 (2003-12-01), Morrow et al.
patent: 2002/0019125 (2002-02-01), Juengling et al.
patent: 102 46 830 (2004-02-01), None
Arnal, Vincent, et al.; “Integration of a 3 Level Cu-SiO2Air Gap Interconnect for Sub 0.1 micron CMOS Technologies”; Proceedings IITC 2001.

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