Latency signal generator and method thereof

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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Details

C713S400000, C713S401000, C365S189050, C365S189150, C365S233100, C365S233150

Reexamination Certificate

active

07958382

ABSTRACT:
A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.

REFERENCES:
patent: 6320818 (2001-11-01), Matsubara
patent: 6662304 (2003-12-01), Keeth et al.
patent: 7170819 (2007-01-01), Szczypinski
patent: 2002/0093871 (2002-07-01), Kwak
patent: 2005-158165 (2005-06-01), None
patent: 2003-0046128 (2003-06-01), None
patent: 10-0532441 (2005-11-01), None

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