Latency circuit using division method related to CAS latency...

Details Latency circuit using division method related to CAS latency... Latency circuit using division method related to CAS latency...

2010-02-01

2011-10-25

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S194000, C365S233100, C365S233110

Reexamination Certificate

active

08045406

ABSTRACT:
A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

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