Latched address multi-chunk write to EEPROM

Details Latched address multi-chunk write to EEPROM Latched address multi-chunk write to EEPROM

2002-11-01

2004-12-07

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C365S185330, C365S189050

Reexamination Certificate

active

06829673

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to data write circuits for memory devices and in particular, to a multi-chunk data write circuit and method for concurrently writing more than one addressable chunk of data at a time to an electrically-erasable and programmable read-only memory (EEPROM).
BACKGROUND OF THE INVENTION
In a conventional EEPROM, data is written one addressable data chunk at a time. Accordingly, a multi-chunk write operation includes several repetitions of providing an address and a data chunk to be written at that address, then programming and verifying the programming of the data chunk into that address. Since the time for programming and verifying the programming of each chunk of data generally far exceeds the time required for providing the address and the data for each chunk of data, such multi-chunk write operations in a conventional EEPROM tend to be very slow.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a multi-chunk write circuit and method for performing multi-chunk write operations to an EEPROM in a significantly faster manner than conventional EEPROM write circuits and methods.
This and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a multi-chunk write circuit which concurrently writes and verifies the writing of multiple chunks of data at a time into an EEPROM, thereby performing multi-chunk write operations significantly faster than conventional EEPROM write circuits which sequentially write a chunk of data at a time into an EEPROM.
Another aspect is a circuit for concurrently writing data into selected ones of a plurality of subarrays of EEPROM cells. Included in the circuit are means for storing a plurality of addresses indicative of locations in the plurality of subarrays of EEPROM cells; a plurality of data registers coupled to the plurality of subarrays of EEPROM cells; and means for sequentially storing addresses into the storing means and corresponding data into the plurality of data registers, and concurrently writing the data stored in the plurality of data registers into the locations in the plurality of subarrays corresponding to the stored addresses.
In another aspect, a method of concurrently writing a plurality of data chunks into an EEPROM, comprises the steps of: sequentially storing the plurality of data chunks into a plurality of data storage means respectively coupled to corresponding subarrays of the EEPROM; providing row and column select signals to row and column decoder means coupled to the corresponding subarrays of the EEPROM; and concurrently writing the plurality of data chunks stored in the plurality of data storage means into the corresponding subarrays of the EEPROM as indicated by the row and column select signals.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4578751 (1986-03-01), Erwin
patent: 4715017 (1987-12-01), Iwahashi
patent: 4752871 (1988-06-01), Sparks et al.
patent: 4931999 (1990-06-01), Umeki
patent: 5043940 (1991-08-01), Harari
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5168468 (1992-12-01), Magome et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5289429 (1994-02-01), Watanabe
patent: 5297148 (1994-03-01), Harari et al.
patent: 5301162 (1994-04-01), Shimizu
patent: 5396468 (1995-03-01), Harari et al.
patent: 5422842 (1995-06-01), Cernea et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5495442 (1996-02-01), Cernea et al.
patent: 5530955 (1996-06-01), Kaneko
patent: 5581510 (1996-12-01), Furusho et al.
patent: 5606532 (1997-02-01), Lambrache et al.
patent: 5644531 (1997-07-01), Kuo et al.
patent: 5691954 (1997-11-01), Ooishi
patent: 5765185 (1998-06-01), Lambrache et al.
patent: 5845313 (1998-12-01), Estakhri et al.
patent: 5907856 (1999-05-01), Estakhri et al.
patent: 5930168 (1999-07-01), Roohparvar
patent: 5930815 (1999-07-01), Estakhri et al.
patent: 6044019 (2000-03-01), Cernea et al.
patent: 6081878 (2000-06-01), Estakhri et al.
patent: 6202138 (2001-03-01), Estakhri et al.
patent: 6397314 (2002-05-01), Estakhri et al.
patent: 6459616 (2002-10-01), Beauchamp et al.

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