Latch-up resistant CMOS structure

Details Latch-up resistant CMOS structure Latch-up resistant CMOS structure

1999-04-14

2001-10-30

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

C438S224000, C438S228000, C438S235000, C438S373000, C438S376000, C438S526000, C257S372000, C257S373000

Reexamination Certificate

active

06309940

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and its fabrication method and, more particularly, to a semiconductor device which avoids latch-up by reducing the shunting resistance between the emitter and base of a parasitic bipolar transistor and the current gain of the base, and its fabrication method.
2. Discussion of Related Art
Latch-up, a generic problem associated with complementary metal oxide semiconductor (hereinafter called CMOS) structures causes undesirable conduction phenomena to occur in the parasitic NPN and PNP bipolar transistors inherent in CMOS structure, for example, malfunction or destruction of the devices due to over-current such as transient pulses.
In scaling down of CMOS integrated circuits, the closer spacing between semiconductor regions, especially, P and N junctions increases the current gain of the parasitic NPN and PNP bipolar transistors and turns on the parasitic SCR (Silicon Controlled Rectifier) structure and latch it into conductivity state. Namely, latch-up occurs.
FIG. 1
is a cross-sectional view of the related art semiconductor device.
Referring to
FIG. 1
, the related art semiconductor device, e.g., CMOS inverter circuit has P well
22
and N well
21
formed in a semiconductor substrate
11
. A field oxide layer
13
is formed to define the active and isolation regions of the device. A heavily doped P type regions
27
and
28
are formed in the N well
21
by using a first gate
37
overlying a gate insulating layer
23
as a mask. A heavily doped N type region of N-well contact
30
is then formed at a predetermined portion in the N well
21
. The heavily doped P type regions
28
and
27
become source and drain regions of P channel FET, respectively. A heavily doped N type regions
25
and
26
are formed in the P well
22
by using a second gate
38
overlying the gate insulating layer
23
as a mask. A heavily doped P type region of P-well contact region
29
is formed at a predetermined portion in the P well
22
. The heavily doped N type regions
25
and
26
become source and drain regions of N channel FET, respectively.
In the CMOS inverter circuit
39
having the above-described structure, the P-well contact region
29
and the source region
25
of N channel FET are connected to a ground terminal V
ss
, while the source region
28
of P channel FET and the N-well contact region
30
are connected to a power source V
DD
. The first and second gates
37
and
38
are connected to an input terminal V
IN
, and the drains
26
and
27
of N channel and P channel FETs being connected to an output terminal V
OUT
.
In operation, a signal applied to the input terminal V
IN
at logic high voltage level will cause the N channel FET to turn on. At the same time, the P channel FET is turned off, such that substantially no current flows between the drain and source regions
27
and
28
of P channel FET.
The output terminal V
OUT
connected to the drain regions
26
and
27
is therefore pulled to the lower supply voltage V
SS
through the N channel FET. The CMOS inverter circuit
39
has thus inverted the input logic high voltage level to an output logic low voltage level.
As shown in
FIG. 1
, the CMOS semiconductor device
39
includes two parasitic bipolar transistors
35
and
36
. The transistor
35
is an NPN bipolar transistor with source region
25
of N channel FET forming its emitter, the P well
22
forming its base and N well
21
forming its collector. The transistor
36
is a PNP bipolar transistor with source region
28
of P channel FET forming its emitter, the N well
21
forming its base and the P well
22
forming its collector.
In normal operation of the CMOS inverter circuit
39
, the transistors
35
and
36
are off and the emitter-base PN junction thereof conducts only a minimal leakage current. However, a voltage drop of over 0.6 volts occurs at the ground terminal Vss momentarily due to an electrostatic discharge (ESD) voltage spike inadvertently applied to the device. This voltage drop causes electrons to be injected from the source region
25
of N channel FET into P well
22
, then the NPN transistor
35
is turned on and the electrons reach the N well
21
.
In a case where the electron current(I) and the resistance(R) between N-well contact region
30
and the source region
28
of P channel FET are high sufficiently, a voltage drop of about 0.6 volts also occurs in a small critical current or N-well current, turning the transistor
36
on. This drop in potential causes holes to be injected into the N well
21
from the source region
28
of P channel PET and reaches the P well
22
.
Furthermore, when the resistance between P-well contact region
29
and the source region
25
of N channel FET is high sufficiently, a voltage drop of about 0.6 volts occurs in a small critical current or P-well current to turn the transistor
35
on. This voltage drop causes electrons to be injected into the P well
22
from the source region
25
. This electron current adds to the initial current and strengthens the positive feed back between PNP and NPN transistors
36
and
35
, respectively, which thus leads to the latch-up condition.
The related art CMOS inverter circuit
39
is, however, disadvantageous in that a voltage drop capable of turning on the bipolar transistors
36
and
35
occurs at a small critical current and the latch-up occurs in a case of the sufficiently high resistance between the N-well contact region
30
and the source region
28
of P channel FET or between the P-well contact region
29
and the source region
25
of N channel FET.
SUMMARY OF THE INVENTION
Accordingly, an objective of the present invention is to provide a semiconductor device which avoids latch-up with the presence of heavily doped region of buried layer formed at a predetermined portion in the wells.
Another objective of the present invention is to provide a method of fabricating the latch-up resistant semiconductor device.
To achieve the first object of the present invention, a semiconductor device includes: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well;
a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.
To achieve the second object of the present invention, a method of fabricating a semiconductor device includes the steps of: forming a field oxide layer on a semiconductor substrate having a first conductivity type where the semiconductor substrate is included first and second MOS transistor regions and first and second contact regions; forming a first well having a second conductivity type in the major surface of the semiconductor substrate having the first MOS transistor region and the first contact region; forming a heavily doped region of buried layer having the second conductivity type at a portion spaced corresponding to the first contact region in the first well; forming a second well having the first conductivity type in the semiconductor substrate having the second MOS transistor region and the second contact region; and forming a heavily doped region of buried layer having the first conductivity type at a portion spaced corresponding to the second contact region in the second well.
It is to be understood that both the foregoing general desc

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