Method of forming an image sensor cell and a CMOS logic...

Details Method of forming an image sensor cell and a CMOS logic... Method of forming an image sensor cell and a CMOS logic...

2000-01-18

2001-02-27

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S279000, C438S210000, C438S229000

Reexamination Certificate

active

06194258

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to integrate the fabrication of an image sensor cell, and of CMOS logic devices, featuring a non-salicided photodiode element.
(2) Description of Prior Art
Image sensor cells are usually comprised of active image sensing elements, such as photodiodes, in addition to adjacent transistor structures, such as transfer gate transistors, and reset transistors. These transistor structures, as well as additional devices used for the control and signal circuits in the peripheral regions of the image sensor cell, or used for peripheral logic circuits, are comprised with complimentary metal oxide semiconductor, (CMOS), devices. Therefore to reduce process cost and complexity, the image sensor cell has also been fabricated using the same CMOS process sequences used for the peripheral CMOS logic circuits This approach however can influence the quality of the photodiode element, of the image sensor cell, if the photodiode element is subjected to traditional CMOS process sequences. For example if a metal silicide layer is formed on the surface of the photodiode element, during the formation of Self-ALigned metal silICIDE, (Salicide), on the gate structure, as well as on the source/drain region of the CMOS logic circuits, unwanted leakages, in the form of dark current generation, as well as degraded signal to noise, (S/N), ratios, of the image sensor cell, can result.
This invention will describe a process sequence used to form salicide layers on all silicon or polysilicon surfaces of deep submicron CMOS logic devices, (where deep submicron refers to CMOS devices fabricated with channel lengths less than 0.25 &mgr;m), in addition to forming salicide on the top surface of a polysilicon gate structure, located in the image sensor cell region, however avoiding salicide formation on the surface of the photodiode element. This selective salicide formation is accomplished without the use of an additional photolithographic masking procedure, using a thin silicon oxide layer to protect the surface of the photodiode element during the salicide formation procedure. A thick organic layer, applied after removal of the thin silicon oxide layer from regions of CMOS logic devices, is etched back allowing only the top surface of a gate structure, located in the image sensor region, to experience the salicide process. This novel process sequence allows the image sensor cell to be formed simultaneously with the high performance logic devices, featuring the desired low dark current generation, and high S/N ratios, as a result of protecting the photodiode element from salicide processing. Prior art, such as Clark et al, in U.S. Pat. No. 5,859,450, describe a process for forming an image sensor cell, but do not use the process sequence described in the present invention to protect the photodiode element from salicide formation. Huang, in U.S. Pat. No. 5,863,820, does describe a fabrication sequence for forming salicide only on elements of logic regions, while protecting regions of memory devices from the same salicide process. However this prior art does not teach the fabrication sequence, detailed in the present invention, in which a thin silicon oxide layer, and a thick organic layer, are patterned to allow salicide formation only on the top surface of a gate structure of an image sensor cell, while protecting the photodiode element of this cell from the same salicide formation procedure.
SUMMARY OF THE INVENTION
It is an object of this invention to integrate the fabrication of an image sensor cell, and logic devices, using a deep submicron CMOS process.
It is another object of this invention to form salicide layers on the polysilicon gate structure, and on the source/drain region, of the logic devices, while the surface of the photodiode element of the image sensor cell remains non-salicided.
It is yet another object of this invention to protect the surface of the photodiode element from the salicide formation process, via use of a thin silicon oxide layer, located overlying the surface of the photodiode element.
It is still yet another object of this invention to use an etched back, thick organic layer, on the thin silicon oxide layer, in a region overlying the photodiode element, allowing the selective removal of the thin silicon oxide layer from the top surface of a polysilicon gate structure, in the image sensor cell, prior to the salicide formation.
In accordance with the present invention a fabrication process for integrating an image sensor cell, and CMOS logic devices, featuring salicided CMOS logic device elements, and a non-salicided photodiode element, of the image sensor cell, has been developed. After formation of polysilicon gate structures, on an underlying gate insulator layer, for both logic and image sensor cell regions, N type, lightly doped, source/drain regions are formed in an area of a P well region, not covered by the polysilicon gate structures. After formation of silicon nitride spacers, on the sides of the polysilicon gate structures, a heavily doped, N type ion implantation procedure is used to create heavily doped source/drain regions, for both CMOS logic devices and for the image sensor cell, in addition to forming the N/P well, photodiode element, for the image sensor cell. A thin silicon oxide layer is deposited, then removed from the logic device region. A thick organic layer is applied, then etched back to expose the thin silicon oxide layer, located on the top surface of the polysilicon gate structure, in the image sensor cell region. After removal of the exposed, thin silicon oxide layer, the thick organic layer is removed, leaving regions of the thin silicon oxide layer only on the surface of the photodiode element, and on the surface of the source/drain regions, of the image sensor cell. Metal silicide is then formed on all exposed silicon surfaces, including the heavily doped source/drain region, and polysilicon gate structure, of the logic device region, and on the polysilicon gate structure of the image sensor cell, while the surface of the photodiode element, and of the heavily doped source/drain region, of the image sensor cell, remain non-salicided. An interlevel insulator layer is deposited, followed by contact openings exposing the salicided polysilicon gate structure, and the salicided heavily doped, source/drain region, of the logic device region, as well as exposing a non-salicide, heavily doped source drain region, located in the image sensor cell. Metal contact structures are then formed in the contact hole openings.


REFERENCES:
patent: 5859450 (1999-01-01), Clark et al.
patent: 5863820 (1999-01-01), Huang
patent: 6023081 (2000-02-01), Drowley et al.
patent: 6040592 (2000-03-01), McDaniel et al.
patent: 6040593 (2000-03-01), Park
patent: 6137127 (2000-02-01), Merrill

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