Latch-up prevention for memory cells

Details Latch-up prevention for memory cells Latch-up prevention for memory cells

2006-03-28

2006-03-28

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S202000, C438S210000

Reexamination Certificate

active

07018889

ABSTRACT:
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCCthrough parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

REFERENCES:
patent: 4609835 (1986-09-01), Sakai et al.
patent: 4805008 (1989-02-01), Yao et al.
patent: 5298782 (1994-03-01), Sundaresan
patent: 5406513 (1995-04-01), Canaris et al.
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5721445 (1998-02-01), Singh et al.
patent: 5804477 (1998-09-01), Lien
patent: 5892263 (1999-04-01), Tachiyama
patent: 5896313 (1999-04-01), Kao et al.
patent: 6005797 (1999-12-01), Porter et al.
patent: 6187618 (2001-02-01), Kao et al.
patent: 6376297 (2002-04-01), Porter et al.
patent: 6642588 (2003-11-01), Porter et al.
patent: 6767784 (2004-07-01), Porter et al.

Affiliated with

Also associated with

Rating

Latch-up prevention for memory cells does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latch-up prevention for memory cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latch-up prevention for memory cells will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3572384