Latch placement technique for reduced clock signal skew

Details Latch placement technique for reduced clock signal skew Latch placement technique for reduced clock signal skew

2006-03-28

2006-03-28

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07020861

ABSTRACT:
A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.

REFERENCES:
patent: 6440780 (2002-08-01), Kimura et al.
patent: 6442739 (2002-08-01), Palermo et al.

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