Latch placement for high performance and low power circuits

Details Latch placement for high performance and low power circuits Latch placement for high performance and low power circuits

2006-12-14

2009-06-16

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07549137

ABSTRACT:
A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.

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Y. Lu et al., “Navigating Registers in Placement for Clock Network Minimization,” ACM Design Automation Conference pp. 176-181 (Jun. 2005).
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G. Venkataraman et al., “Integrated Placement and Skew Optimization for Rotary Clocking,” European Design Automation Association (2006).
N. Venkateswaran et al., “Clock-Skew Constrained Placement for Row Based Designs,” International Conference of Computer Design (1998).

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