Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-11
2002-11-12
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S594000
Reexamination Certificate
active
06479349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of fabricating a nonvolatile semiconductor memory device having a floating gate, and a control gate formed so as to overlap the floating gate. More particularly, the present invention relates to a method in which erasing efficiency is prevented from being lowered when data erasing operation is repeated by drawing out electric charges (electrons) accumulated on a floating gate to the control gate side, so that W/E(Writing/Erasig) cycle of memory cells is elongated.
2. Desription of the Related Art
In an electrically erasable nonvolatile semiconductor memory device, especially, programmable ROM (EEPROM: Electrically erasable and programmable ROM), having memory cells each composed of a single transistor, each of the memory cells is formed from a double gate structure transistor having a floating gate, and a control gate. In the case of such a double gate structure memory cell transistor, data writing is performed when hot electrons generated in the drain region side of the floating gate are accelerated and injected into the floating gate. Further, data erasing operation is performed when electric charges are drawn out from the floating gate to the control gate by F-N tunneling (Fowler-Nordheim tunneling).
FIG. 13
is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate, and
FIG. 14
is a sectional view taken along the X—X line in FIG.
13
. These drawings show a split gate structure in which a control gate and a floating gate are disposed side by side.
A plurality of strip-like isolation regions
2
are formed of oxide films (LOCOS) so as to be oxidized selectively thicker than other region in a surface region of a P-type silicon substrate
1
, so that a device region is isolated. Each floating gate
4
is disposed on an oxide film
3
so as to bridge adjacent isolation regions
2
. The floating gates
4
are disposed independently so that one floating gate
4
corresponds to one memory cell. Further, a selective oxide film
5
on each floating gate
4
is formed thick in the center portion of the floating gate
4
by a selective oxidizing method so that the floating gate
4
has an acute end portion. This fact makes electric field concentration occur easily in the end portion of the floating gate
4
when a data erasing operation is carried out.
On the silicon substrate
1
on which the plurality of floating gates
4
are disposed, control gates
6
are disposed so that one control gate
6
corresponds to one row of floating gates
4
. The control gates
6
are disposed so that a part of each control gate
6
overlaps floating gates
4
and the residual part faces the silicon substrate
1
through the oxide film
3
. Further, these floating gates
4
and control gates
6
are disposed so that adjacent rows are plane-symmetrical with each other.
N-type drain regions
7
and N-type source regions
8
are formed in a substrate region between the control gates
6
and in a substrate region between the floating gates
4
, respectively. The drain regions
7
are surrounded by isolation regions
2
between adjacent control gates
6
so as to be independent of each other. The source regions
8
are formed so as to be continuous in the direction of extension of each control gate
6
. A memory cell transistor is constituted by a floating gate
4
, a control gate
6
, a drain region
7
and a source region
8
.
Aluminum wirings
10
are disposed on the oxide film
9
so as to intersect the control gates
6
. The aluminum wirings
10
are connected to the drain regions
7
through contact holes
11
. Further, the row of control gates
6
serves as a word line, and the row of source regions
8
parallel with the row of control gates
6
serves as a source line. Each of the aluminum wirings
10
connected to the drain regions
7
serves as a bit line.
In the case of such a double gate structure memory cell transistor, the value of “source-drain ON resistance” varies in accordance with the quantity of electric charges injected into the floating gate
4
. Therefore, electric charges are injected into the floating gate
4
selectively to make the value of ON resistance of a specific memory cell transistor change so that the difference in operating characteristic of memory cell transistors caused thereby is related to data to be stored.
Incidentally, electrically insulating films
3
for electrically insulating the silicon substrate
1
, floating gates
4
and control gates
6
from one another are constituted by three types of silicon oxide films
3
a
to
3
c
as shown in FIG.
15
. The first silicon oxide film
3
a
is a gate insulating film formed by thermal oxidation of a surface of the silicon substrate
1
. The first silicon oxide film
3
a
electrically insulates the silicon substrate
1
and the floating gate
4
from each other. Incidentally, the first silicon oxide film
3
a
is configured so that a predetermined amount of silicon oxide film
3
a
except the lower surface of the floating gate
4
is removed by etching at the time of patterning of the floating gate
4
for forming the floating gate
4
.
Further, the second silicon oxide film
3
b
is a CVD (chemical vapor deposition) oxide film which is formed through chemical vapor-phase growth by a CVD method so that the floating gate
4
is coated with the second silicon oxide film
3
b
when the second silicon oxide film
3
b
is formed on the silicon substrate
1
.
Further, the third silicon oxide film
3
c
is formed in a side wall portion of the floating gate
4
and in a surface of the silicon substrate
1
when the silicon substrate
1
is thermally oxidized after the second silicon oxide film
3
b
is formed. These first, second and third silicon oxide films
3
a
to
3
c
form a three-layer structure for electrically insulating the silicon substrate
1
and the control gate
6
from each other and electrically insulating the floating gate
4
and the control gate
6
from each other. That is, the floating gate
4
is coated with the three-layer structure electrically insulating film
3
to thereby heighten the withstand voltage between the floating gate
4
and the control gate
6
to prevent error in memory cell Writing/Erasing, which is called write/read disturbance.
The above description concerning the related art is disclosed in JP-A-8-236647 filed by the Applicant of this application.
According to the above JP-A-8-236647, a tunnel oxide film (a part of oxide film
3
) is optimized so that the number of data rewrites (W/E cycle) by which data Writing/Erasing in a memory cell transistor can be repeated is increased. The tunnel oxide film becomes, however, insufficient to satisfy the recent stronger requirement for W/E cycle.
FIG. 8
shows the results of measurement of W/E cycle in the conventional device having the aforementioned configuration.
FIG. 8
shows a state in which the measured memory cell current (axis of ordinate) in an erased memory cell decreases as the number of data rewrites (axis of abscissa) by which data is rewritten increases. As shown in
FIG. 8
, in the nonvolatile semiconductor memory device fabricated by the conventional process, the number of data rewrites by which rewriting can be repeated before the cell current has decreased to reach a critical judgeable level (for example, about 30% of the initial value 100 &mgr;A of the memory cell current in the erased memory cell: memory cell current 30 &mgr;A) is about 70000. In a general programmable memory, about 100000 is required as the number of data rewrites of repetitions of the data W/E cycle. Accordingly, the number of data rewrites of repetitions of about 70000 is insufficient and it is required to be increased more.
Therefore, the Applicant of this application has aimed at optimizing the configuration of a tunnel oxide film formed between a floating gate and a control gate to attain a further improvement of W/E cycle of a memory cell transistor and has
Kurooka Kazumi
Oya Toshiharu
Armstrong Westerman & Hattori, LLP
Ho Hoai
Le Thao P
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