Laser thermal process for fabricating field-effect transistors

Details Laser thermal process for fabricating field-effect transistors Laser thermal process for fabricating field-effect transistors

2000-10-27

2002-04-02

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000, C438S305000, C438S306000, C438S535000, C438S530000, C438S527000, C438S514000

Reexamination Certificate

active

06365476

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to processes for fabricating semiconductor field-effect transistors, and in particular to such processes involving laser thermal processing.
BACKGROUND OF THE INVENTION
Laser thermal processing (LTP) involves using short pulses of laser radiation (e.g., on the order of nanoseconds to tens of nanoseconds) to thermally anneal and activate dopants in a semiconductor. The pulses of laser radiation provide sufficient heat to briefly melt the doped semiconductor, which allows the dopants to diffuse within the molten region. When the semiconductor cools, it recrystallizes with the electrically active dopants occupying lattice sites within the crystal.
LTP techniques can be used to form junctions and source and drain (S/D) extension regions of a field-effect transistor (FET). Junctions formed using LTP techniques are shallow, abrupt and have low resistance, which are all very desirable device characteristics. In addition, because of the extremely high heating and cooling rate involved in LTP (10
6
−10
12
° K/s), a meta-stable state can be established where dopant activation above the solid solubility limit occurs. These properties allow a transistor to be scaled to a smaller dimension with improved performance.
Incorporated by reference herein is the article by Talwar et al., “Ultra-Shallow, Abrupt, and Highly Activated Junctions by Low-energy Ion Implantation and Laser Annealing,” Proceedings of the 13
th
International Conference on Ion Implantation Technology, pp. 1171-1174 (1999), the article by Talwar et al., “Laser Thermal Processing for Shallow-Junction and Silicide Formation,” Proceedings of the SPIE, Microelectronic Device Technology II, volume 3506, p. 74-81 (1998), and the article by Goto et al., “Ultra-Low Contact Resistance for Deca-nm MOSFETs by Laser Annealing,” IEDM Digest, paper 20.7.1, pp. 931-933 (1999). These articles describe applications of LTP to semiconductor fabrication. Also incorporated by reference is U.S. Pat. No. 5,956,603, entitled “Gas Immersion Laser Annealing Process Suitable for Use in the Fabrication of Reduced-Dimension Integrated Circuits,” and U.S. Pat. No. 5,908,307, entitled “Fabrication Processes for Reduced-Dimension FET Devices.”
Unfortunately, LTP techniques cannot be directly inserted into the conventional complimentary metal-oxide-semiconductor (CMOS) fabrication process flow. This is because in the conventional process flow, deep source/drain regions need to be formed to make the contacts so that the transistors can be connected to each other to form a functional circuit. The formation of deep source/drain regions requires a high-temperature rapid thermal annealing (RTA) step to activate the implanted dopant. The RTA process is typically performed at a temperature of about 1000° C. for a duration of several tens of seconds. The RTA process is also used to activate and diffuse the dopants in the poly gate to decrease the poly resistance and eliminate the poly depletion problem. Such high RTA temperatures, however, cause the dopants in the laser-annealed shallow source/drain regions to out-diffuse into the silicon substrate. This results in deeper and less abrupt junctions, which degrades device performance. In addition, electrically active dopants in a meta-stable state (i.e., above the solid-solubility limit) can also deactivate (i.e., precipitate and become electrically inactive), resulting in higher electrical resistance and thus diminished device performance.
The prior art contains a technique that can be used to avoid the degradation of LTP junctions caused by post-LTP thermal process. The idea is to limit the post-LTP thermal budget by forming deep source/drain regions before LTP of the shallow source/drain extensions. This can be done using a so-called disposable spacer process (DSP), as described in the article by Yu et al, “70 nm MOSFET with Ultra-Shallow, Abrupt, and Super-Doped S/D Extension Implemented by Laser Thermal Process,” IEDM Digest, paper 20.4.1, pp. 509-511 (1999). In the process described in the Yu article, an additional dielectric layer is deposited and etched back to form a disposable spacer. This spacer is used to self-align the deep source/drain dopant implant and is subsequently removed. While working devices have been demonstrated with this approach, it requires additional steps, which add to the process complexity and thus increases the manufacturing costs.
Accordingly, it would be desirable to have a non-complex LTP-based CMOS process flow that does not compromise the above-mentioned desired LTP junction characteristics.
SUMMARY OF THE INVENTION
The present invention relates to processes of fabricating semiconductor field-effect transistors, and in particular to such processes involving laser thermal processing.
Accordingly, a first aspect of the present invention is a process for fabricating a field-effect transistor semiconductor device from a semiconductor substrate having an upper surface, spaced apart shallow trench isolations, and a gate formed on the upper surface between the shallow trench isolations. The process includes the step of forming removable first dielectric spacers on respective sides of the gate. The next step involves implanting dopants into the substrate in respective first and second regions between the spacers and the shallow isolation trenches. The third step involves annealing the first and second regions to form an active deep source and an active deep drain. The next step involves removing the removable spacers. A blanket pre-amorphization implant is then performed to form amorphized source and drain regions that include extension regions that extend up to the gate. The next step then includes depositing at least one layer of material (referred to as a “stack” herein) over at least the source and drain extensions, wherein the stack is opaque to a select wavelength of laser radiation. The next step is then irradiating the stack with laser radiation having the select wavelength so as to selectively melt the amorphized source and drain extension regions but not the underlying crystalline substrate. This LTP step causes diffusion of dopants from the deep source and drain into the source and drain extensions. The next step is the removal of the stack.
A second aspect of the present invention involves completing the formation of the MOSFET structure by forming first and second permanent dielectric spacers on the first and second sides of the gate, respectively, and then forming electrical contacts atop the gate, the source and the drain.
A third aspect of the present invention is a MOSFET device product-by-process, made using the process summarized immediately above and described in more detail below.


REFERENCES:
patent: 5270227 (1993-12-01), Kameyama et al.
patent: 5399506 (1995-03-01), Tsukamoto
patent: 5908307 (1999-06-01), Hawryluk et al.
patent: 5956603 (1999-09-01), Talwar et al.
patent: 6013546 (2000-01-01), Gardner et al.
patent: 6051483 (2000-04-01), Lee et al.
patent: 6194748 (2001-02-01), Yu
patent: 6284630 (2001-09-01), Yu
patent: 6287925 (2001-09-01), Yu
patent: 6306714 (2001-09-01), Pan et al.
patent: 6297117 (2001-10-01), Yu
patent: 6309937 (2001-10-01), Lin
Talwar et al., Ultra-Shallow, Abrupt, and Highly Activated Junctions by Low-energy Ion Implantation Technology, Proceedings of the 13thInternational Conference on Ion Implantation Technology, 1999, pp. 1171-1174.
Talwar, et al., Laser Thermal Processing for Shallow-Junction and Silicide Formation, Proceedings of the SPIE, Microelectronic Device Technology II, vol. 3506, pp. 74-81, 1998.
Goto, et al., Ultra-Low Contact Resistance for Deca-nm MOSFETs by Laser Annealing, IEDM Digest, papar 20.7.1, pp. 931-933, 1999.
Yu, et al., 70nm MOSFET with Ultra-Shallow, Abrupt, and Super-Doped S/D Extension Implemented by Laser Thermal Process (LTP), IEDM Digest, paper 20.4.1, pp. 509-511, 1999.

Affiliated with

Also associated with

Rating

Laser thermal process for fabricating field-effect transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Laser thermal process for fabricating field-effect transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Laser thermal process for fabricating field-effect transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2891835