Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – By application of corpuscular or electromagnetic radiation
Reexamination Certificate
2002-06-07
2003-10-14
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
By application of corpuscular or electromagnetic radiation
Reexamination Certificate
active
06632729
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the manufacture of semiconductor devices which include a high-k dielectric gate oxide layer and semiconductor devices obtained thereby. More specifically, the present invention relates to an improved method for performing thermal annealing of high-k dielectric oxide layers and to MOSFET semiconductor devices obtained thereby.
BACKGROUND OF THE INVENTION
The performance of MOSFET-based semiconductor devices is improved by increasing the capacitance between the gate electrode and the underlying channel region within the semiconductor substrate. Typically, the capacitance is increased by decreasing the thickness of the gate dielectric layer, typically an oxide layer such as a silicon oxide, to below about 100 Å. Currently, silicon oxide, e.g., SiO
2
, gate dielectric layer thicknesses are approaching about 40 Å or less. However, the utility of silicon oxide as a gate dielectric is severely limited at such reduced thicknesses, e.g., due to direct tunneling through the gate dielectric layer to the underlying channel region, thereby increasing the gate-to-channel leakage current and an increase in power consumption.
Inasmuch as further reduction in the silicon oxide gate dielectric thickness is impractical in view of the above increase in gate-to-channel leakage current, various approaches have been investigated for reducing the gate-to-channel leakage current while maintaining a thin SiO
2
“equivalent thickness”, i.e., the thickness of a non-SiO
2
dielectric layer determined by multiplying a given SiO
2
thickness by the ratio of the dielectric constant of the non-SiO
2
dielectric to that of SiO
2
, i.e., k
non-SiO2
/k
SiO2
. Thus, one approach which has been investigated is the use of materials with dielectric constants higher than that of silicon oxide materials as gate dielectric materials, whereby the “high-k” dielectric materials, i.e., materials with dielectric constants of about 5 or above, replace the conventional silicon oxide-based “low-k” dielectric materials with dielectric constants of about 4 or below. The increased capacitance k (or permittivity &egr;) of the gate dielectric material advantageously results in an increase in the gate-to-channel capacitance, which in turn, results in improved device performance. Since the capacitance C is proportional to the permittivity &egr; of the gate dielectric material divided by the thickness t of the gate dielectric layer, it is evident that the use of a high-k (or high-&egr;) material permits use of thicker gate dielectric layers, i.e., >40 Å, whereby both greater capacitance and device speed are obtained with less gate-to-channel leakage current.
Typically, high-k dielectric materials, i.e., with k≧5, suitable for use as gate dielectric layers in the manufacture of semiconductor devices, are formed with a physical thickness from about 40 to about 500 Å, typically 40-100 Å (or a SiO
2
equivalent thickness less than about 40 Å), and comprise metal and oxygen-containing material including at least one dielectric material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides. Suitable metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, and yttrium oxide; suitable metal silicates include zirconium silicate, and hafnium silicate; suitable metal aluminates include hafnium aluminate and lanthanum aluminate; suitable metal titanates include lead titanate, barium titanate, strontium titanate, and barium strontium titanate; suitable metal zirconates include lead zirconate; and suitable ferroelectric and/or ternary metal oxides include PST (PbSc
x
Ta
1−x
O
3
), PZN (PbZn
x
Nb
1−x
O
3
), PZT (PbZr
x
Ti
1−x
O
3
), and PMN (PbMg
x
Nb
1−x
O
3
). Preferred methods for deposition of the high-k metal oxide layer include various chemical vapor deposition (CVD) methods and physical vapor deposition (PVD) methods such as sputtering, vacuum evaporation, etc.
However, the use of high-k metal oxide-based materials as gate dielectric layers for MOSFET semiconductor devices incurs a disadvantage in that such high-k dielectric materials inevitably are formed to contain a much greater number of bulk traps and interface traps (at the interface between the gate dielectric layer and the underlying semiconductor substrate) than gate dielectric layers comprising thermally grown, low-k SiO
2
. In particular, the presence of traps at the interface between the high-k gate dielectric layer and the underlying semiconductor substrate decreases electron mobility in the channel region of the semiconductor substrate beneath the gate dielectric layer. The traps also adversely affect both the sub-threshold slope and threshold voltage (V
t
) operation of the devices.
One approach for improving gate dielectric performance of high-k dielectrics is to limit the effects of the bulk and interface traps by post-dielectric deposition annealing for deactivating the traps, as by rapid thermal annealing (RTA). However, when annealing for trap deactivation is performed by RTA, the structure comprised of a semiconductor substrate, high-k gate dielectric oxide layer, and overlying gate electrode is maintained at an elevated temperature for a sufficiently long interval such that oxygen diffuses from the high-k dielectric oxide layer into the underlying semiconductor layer to form a layer of oxidized semiconductor material at the interface between the gate oxide layer and the semiconductor substrate. Illustratively, and with reference to
FIG. 1
, when the substrate is a silicon (Si) or Si-containing substrate, a low-k silicon oxide layer, typically a SiO
2
layer, is formed at the interface between the semiconductor substrate and the high-k gate oxide layer. The presence of the low-k SiO
2
layer beneath the high-k gate oxide layer disadvantageously increases the Effective Oxide Thickness (EOT) of the gate oxide layer, thereby mitigating the benefit attributable to the thin equivalent SiO
2
layer thickness provided by use of the high-k dielectric oxide layer.
Accordingly, there exists a need for improved methodology for performing simple, reliable, and rapid annealing of high-k dielectric oxide layers for trap deactivation, performed as part of a process sequence for the manufacture of high performance MOSFET-based semiconductor devices, e.g., NMOS and PMOS transistors and CMOS devices, which methodology avoids the drawbacks and disadvantages associated with the conventionally utilized RTA processing for trap deactivation and provides, inter alia, MOSFET devices with increased gate-to-channel capacitance and performance benefits/enhancements associated therewith.
The present invention, wherein annealing for deactivation of bulk and interface traps associated with gate dielectric layers composed of high-k dielectric oxide materials, e.g., metal oxides, is performed by a laser thermal annealing (LTA) process which eliminates, or at least substantially reduces, oxygen out-diffusion from the high-k dielectric oxide layer resulting in deleterious formation of a layer of low-k oxidized semiconductor material at the gate dielectric layer/semiconductor substrate interface, effectively addresses and solves the need for improved methodology for the manufacture of high performance MOSFET devices with increased gate-to-channel capacitance and performance benefits/enhancements associated therewith. Further, the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components requiring the formation of high quality, low trap density, high-k dielectric oxide layers on semiconductor substrates.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for manufacturing a semiconductor device.
Another advantage
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