Laser method for forming vias

Details Laser method for forming vias Laser method for forming vias

2001-06-05

2002-08-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S118000, C438S612000, C438S613000

Reexamination Certificate

active

06429049

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90105771, filed Mar. 13, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for forming vias. More particularly, the invention relates to a method for forming vias that can be implemented in semiconductor packaging.
2. Description of the Related Art
As electronic technology progresses, the emphasis is more particularly made to the miniaturization of electronic products. This miniaturization results in a structure of electronic products that is more complicated. In electronic industries, packaging of electronic devices thus requires carriers which density of inputs/outputs and circuit layout must be higher.
To meet the requirement of high-density carrier, printed circuit board (PCB) type carriers are thus commonly used as substrate in packaging. Conventionally, a printed circuit board is composed of a multiple of patterned trace layers and insulating layers alternately stacked. The insulating layers are provided with a plurality of conductive vias to connect the different patterned trace layers with one another.
Referring to
FIG. 1
, a flow diagram schematically shows the different steps in a process for forming vias, illustrated by cross-sectional views of FIG.
2
through FIG.
5
. More particularly, FIG.
2
through
FIG. 5
schematically illustrate a conventional process for forming vias used in cavity down packaging.
Referring to
FIG. 2
, a heat sink
112
, usually made of copper, is first provided (step
100
of FIG.
1
). A local oxidization of a surface of the heat sink is then performed to form copper oxide (CuO) films
114
(step
102
). Then, a plating is performed to form a silver or gold layer
121
on the surface of the heat sink that was not oxidized (step
106
). The locations on the surface of the heat sink onto which oxidization and plating have to be performed being predetermined, the order according to which local oxidization and local plating should be performed can thus be indifferently chosen. Then, a substrate
115
is bonded onto the heat sink
112
(step
104
). The substrate
115
comprises a patterned trace layer
118
and an insulating layer
116
onto which is bonded the heat sink at the copper oxide locations. The insulating layer
116
has a plurality of through holes
116
a
therein that expose the region of the silver or gold layer
121
when the substrate
115
is arranged on the heat sink
112
.
As described above, the heat sink
112
is usually made of copper. When the oxidization is performed on the surface of the heat sink, the thus-formed copper oxide is acicular. The purpose of the oxidization is thus to improve the bonding of the substrate
115
onto the heat sink
112
. Because the substrate
115
is locally bonded onto the heat sink
112
, only corresponding local portions of the heat sink
112
are thus oxidized. The local oxidization is typically performed by forming a mask covering the surface of the heat sink, the formed mask comprising openings where the surface of the heat sink is to be oxidized (not shown). Then, a heating in a highly oxygenated environment forms a copper oxide film where the surface of the heat sink is exposed. The mask is then removed.
Referring to
FIG. 3
, a chip
126
is bonded onto the heat sink and connected to a plurality of chip fingers
120
, connected to the patterned trace layer
118
of the substrate
115
, via a plurality of bonding wires
124
(step
104
). Then, a molding compound
128
encapsulates the chip
126
and the bonding wires
124
.
Referring to FIG.
4
and
FIG. 5
, a plurality of vias are then formed by first filling the holes
116
a
with a solder material by screen printing (step
108
), and subsequently, reflowing the solder material by a heating in a furnace to about 138° C. (step
110
). The thus-formed vias are connected to the patterned trace layer
118
and terminate in a plurality of ball pads for a subsequent attachment of solder balls thereon to complete the cavity down packaging.
The above-described conventional process necessitates a solder screen printing and a heating in a furnace to form the vias. Such a process for forming vias is complicated and increases the manufacturing cost. Thus, one may wish a simpler method.
SUMMARY OF THE INVENTION
One major aspect of the present invention is to provide a laser method for forming vias in which the disposing of solder balls and use of laser beam advantageously substitute for the conventional solder screen printing and furnace heating to obtain a simplified manufacturing process.
To attain the foregoing and other aspects, the present invention, according to a first preferred embodiment, provides a laser method for forming vias, suitable to cavity down packaging, the laser method comprising: providing a heat sink; oxidizing a surface of the heat sink to form an oxide layer thereon; bonding a substrate onto the heat sink, wherein the substrate comprises at least a patterned trace layer and an insulating layer onto which is bonded the heat sink, the insulating layer having a plurality of through holes that expose the oxide layer of the substrate; removing the oxide layer exposed through the through holes by laser beam; disposing a plurality of solder balls respectively in the through holes; and heating by laser beam the solder balls to fill up the through holes, thereby forming a plurality of vias connected to the patterned trace layer.
To attain the foregoing and other aspects, the present invention, according to a second preferred embodiment, provides a laser method for forming vias, used in a built-up laminated substrate, the laser method comprising: providing a substrate that comprises a first patterned trace layer and a first insulating layer; oxidizing a surface of the first patterned trace layer to form an oxide layer thereon; bonding a laminate onto the substrate, wherein the laminate comprises a second patterned trace layer and a second insulating layer onto which is bonded the substrate, the second insulating layer having a plurality of through holes that expose the oxide layer of the substrate; removing the oxide layer exposed through the through holes by laser beam; disposing a plurality of solder balls respectively in the through holes; and heating by laser beam the solder balls to fill up the through holes, thereby forming a plurality of vias that connect the first patterned trace layer to the second patterned trace layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5821624 (1998-10-01), Pasch
patent: 5854085 (1998-12-01), Raab et al.
patent: 5890915 (1999-04-01), Reylek
patent: 5919329 (1999-07-01), Banks et al.
patent: 5970319 (1999-10-01), Banks et al.
patent: 6015722 (2000-01-01), Banks et al.
patent: 6052287 (2000-04-01), Palmer et al.
patent: 6165885 (2000-12-01), Gaynes et al.

Affiliated with

Also associated with

Rating

Laser method for forming vias does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Laser method for forming vias, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Laser method for forming vias will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2958367