Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-06
2003-01-21
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S215000, C365S175000
Reexamination Certificate
active
06509236
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for laser fuseblow protection in silicon-on-insulator (SOI) transistors.
DESCRIPTION OF THE RELATED ART
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
As shown in
FIG. 1
, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon dioxide (SiO
2
) or glass, and a MOS transistor built on top of this structure. The SOI FET includes a body (B), a gate (G), a drain (D) and a source (S). The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. With SOI technology faster MOS transistors can be manufactured resulting in higher performance semiconductors for faster electronic devices.
In a conventional, bulk silicon process, the transistors are built in the top surface of a relatively thick mass of silicon. During a laser fuseblow process, energy that is imparted to the transistors has this thick silicon in which to dissipate this energy. SOI transistors are built on the thin layer of silicon placed on top of a thicker insulator as shown in FIG.
1
. Damage to the SOI transistor devices can occur due to the decreased ability to dissipate the resulting charge build up form the laser fuseblow process in the thin layer of silicon.
A need exists for a mechanism for protecting SOI transistors from an excess voltage and charge that can be built up during a laser fuseblow process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method and apparatus for laser fuseblow protection in silicon-on-insulator (SOI) transistors. Other important objects of the present invention are to provide such a method and apparatus for laser fuseblow protection in silicon-on-insulator (SOI) transistors substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for laser fuseblow protection in transistors, such as silicon-on-insulator (SOI) transistors. The transistors are connected to a fuse. A pair of diodes are connected in series between a high supply and ground. A common connection of the series connected pair of diodes is connected to a common connection of the fuse and transistors. A charge is shunted to the high supply or ground by the pair of diodes with a first voltage a set value above the high supply and a second voltage a set value below the ground.
In accordance with features of the invention, a pair of protection diodes are provided on each side of the fuse with transistors. The transistors are either connected to one side of the fuse or to both sides of the fuse.
REFERENCES:
patent: 5986862 (1999-11-01), Kim
patent: 6043609 (2000-03-01), George et al.
patent: 6112275 (2000-08-01), Curry et al.
patent: 6246625 (2001-06-01), Yamagata et al.
patent: 6262919 (2001-07-01), Chou
Effect of Protection Diodes on the Behavior of CMOS Gates in the presnece of Supply Dips Hassanein H. Amer Canadian Conference of Electrical and Computer Engineering 1997 IEEE 1997 pp. 536-539 vol. 2.*
PROM Fuse Design Scales to sub-0.25 mircon Gail Robinson Electronic Engineering Times Sep. 29, 1997 p. 44.
Aipperspach Anthony Gus
Christensen Todd Alan
International Business Machines - Corporation
Meier Stephen D.
Pennington Joan
Perkins Pamela E
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