Large value capacitor

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156648, 148175, 357 14, 357 15, 357 23, 357 55, 357 60, H01L 2704, H01L 2904, H01L 2992

Patent

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040178854

ABSTRACT:
Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate by orientation dependent etches and utilizing the sidewalls of the grooves as surface. Groove depth is limited to a predetermined value by etching time, geometrical constraints, or by etch stops. This provides for precise control of capacitance values on a batch or commercial basis. Increases up to at least 100-fold in capacitance as compared to a flat capacitor structure as possible. A thin layer of dielectric is formed over the increased surface area, and thereafter a conducting layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may also be formed.

REFERENCES:
patent: 2841508 (1958-07-01), Roup et al.
patent: 3460050 (1969-08-01), Hellstrom
patent: 3579057 (1971-05-01), Stoller
patent: 3586925 (1971-06-01), Collard
patent: 3639814 (1972-02-01), Engbert
patent: 3745508 (1973-07-01), Bruder et al.

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