Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1978-12-26
1980-12-09
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
G11C 800
Patent
active
042388422
ABSTRACT:
A computer paging store memory utilizing line addressable random access memories (LARAM) including charge coupled device (CCD) shift registers in which data is read out of the memory for utilization in a block storage memory without loss of refresh time due to the refresh of individual CCD shift registers. The memory is organized as a number of parallel-connected memory storage units, each of which includes a separate interface logic, a refresh control and a number of memory array units, each of which in turn is constructed of LARAM devices, each of which must be refreshed within a predetermined time interval. Data is normally read out from the LARAM devices one at a time in sequence. During the readout operation, a detection is continuously made which determines whether the next LARAM device in sequence must be refreshed during the subsequent readout time period. If a refresh operation is required, the selection sequence is reordered enabling the refreshing operation to occur while the data transfer comes from another element.
REFERENCES:
patent: 4084154 (1978-04-01), Panigrahi
patent: 4112513 (1978-09-01), Elsner
Barsuhn et al., Refresh System for Dynamic Hierarchy Storages, IBM Tech. Disc. Bul., vol. 16, No. 4, 9/73, p. 1074.
Hecker Stuart N.
IBM Corporation
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