Lading plug contact pattern for DRAM application

Details Lading plug contact pattern for DRAM application Lading plug contact pattern for DRAM application

2000-07-18

2001-02-13

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000

Reexamination Certificate

active

06187627

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the fabrication of semiconductor devices, and more particularly to a method for forming a landing plug contact in a memory device.
2. Description of the Related Arts
In DRAM fabrication, even though the DRAM technology is progressing, a simple rectangular pattern shown in
FIG. 1A
is being widely used for the active area formed by Shallow Trench Isolation (STI). However, there is a bitline and node contact (CB and CN) landing problem when using the simple rectangular active area pattern in the capacitor over bitline (COB) structure. An extended landing pad method and twisted bitline technology has been proposed to address the above problem, but they suffer from other problems. In the extended landing pad method, there is a photolithography limitation due to the close packed unsymmetrical contact pattern and small contact dimensions.
In the twisted bitline technology, the increased bitline-to-bitline coupling capacitance results in degradation of the retention time.
Recently, a method using an island-shaped mask pattern assisted by CMP is provided in “A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond”, Y.Kohyama et al., Symposium on VLSI Technology Digest of Technical Papers, p. 17, 1997. It is explained in detail.
FIGS.
1
~
4
are views illustrating the steps of the method. FIGS.
1
B~
4
B and FIGS.
1
C~
4
C are the cross-sectional views derived by cutting FIGS.
1
A~
4
A along the lines AA′ and BB′, respectively.
Referring to
FIGS. 1A
,
1
B and
1
C, a substrate
10
is provided, and active areas
12
and an isolation area
14
are formed thereon by STI with the simple rectangular active area pattern.
Referring to
FIGS. 2A
,
2
B and
2
C, by ion implantation, doped regions
16
are formed for the source and drain regions of the devices. Then, a gate oxide
18
, a polysilicon layer
20
, a metallic layer
22
and a nitride layer
24
are deposited sequentially. The gate oxide
18
, polysilicon layer
20
and metallic layer
22
are 20 Å~50 Å, 500 Å~1500 Å and 500 Å~1500 Å in thickness, respectively. The metallic layer
22
used as wordline is composed of W or WSi
2
, the nitride layer
24
used as isolation layer is composed of SiN, and the polysilicon layer
20
is used as gate. Afterward, strip-shaped stacked layers
25
composed of gate
20
(the polysilicon layer), wordline
22
(the metallic layer) and isolation layer
24
(the nitride layer) are formed by conventional photolithography and etching. Thus, stacked layers
25
stretch over the active areas
12
. Then, a covering isolation film
26
composed of SiN and an isolation layer
28
composed of BPSG are deposited. The isolation layer
28
is ground by CMP so that the isolation layer
28
and the stacked layers
25
have a joint plane surface.
In
FIGS. 3A
,
3
B and
3
C, the isolation layer
28
is etched with island-shaped rectangular patterns
30
. The island-shaped rectangular patterns
30
stretch over the stacked layers
25
and mask the isolation layer
28
therebeneath during etching. Consequently, bitline contacts
32
A and node contacts
32
B are formed by self alignment contact etch technology and the bitline contacts
32
A are longer than the node contacts
32
B in length.
In
FIGS. 4A
,
4
B and
4
C, a conducting layer
34
composed of W or polysilicon is deposited and ground by CMP so that the conducting layer
34
and the stacked layers
25
have a joint plane surface.
The above method eliminates the problems in the extended landing pad method and twisted bitline technology, but results in a large leakage current and bitline-to-wordline coupling capacitance due to the long bitline contacts.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for forming reduced coupling capacitance bitline contacts in a memory device.
To accomplish the above objective, the present invention provides a method of fabricating a semiconductor device having a landing plug. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the worlines. Second, a pattern is defined and the isolation layer masked with the pattern is etched for the formation of bitline and node contacts, wherein the pattern has a protrusion which shortens the length of the bitline contacts formed thereby. Finally, all the contacts are filled with a conducting layer.
Wherein, the pattern is a T-shaped island pattern or a cross-shaped island pattern.
The bitline contacts formed by the method provided in the invention are shorter than those formed by the above-mentioned prior art. Therefore, a large leakage current and a large bitline-to-wordline coupling capacitance no longer exist.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description which makes reference to the accompanying drawings. dr
DESCRIPTION OF THE DRAWINGS
FIGS. 1A through 4A
are plan views illustrating the steps of a conventional method for fabricating a semiconductor memory device;
FIGS. 1B through 4B
are cross-sectional views illustrating the steps of a conventional method for fabricating a semiconductor memory device;
FIGS. 1C through 4C
are cross-sectional views illustrating the steps of a conventional method for fabricating a semiconductor memory device;
FIGS. 5A and 6A
are plan views illustrating the steps of the method for fabricating a semiconductor memory device according to the invention;
FIGS. 5B and 6B
are cross-sectional views illustrating the steps of the method for fabricating a semiconductor memory device according to the invention;
FIGS. 5C and 6C
are cross-sectional views illustrating the steps of the method for fabricating a semiconductor memory device according to the invention; and
FIG. 7
is a plan view illustrating cross-shaped island patterns.


REFERENCES:
patent: 6136645 (2000-10-01), Yang et al.
patent: 6140180 (2000-10-01), Hong

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