JTAG testing arrangement

Details JTAG testing arrangement JTAG testing arrangement

2001-09-05

2004-10-19

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06807644

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to JTAG testing, and more particularly to widening the area where JTAG testing can be applied.
A generally used standard IEEE 1149.1, also known as JTAG (Joint Test Action Group) according to the consortium that prepared the standard, has been created for testing different circuit boards and components connected thereto as well as integrated circuits. The JTAG is a boundary scan method, in which an input signal is fed into a boundary pin of the circuit board and an output signal is measured from another boundary pin. The basic idea of the JTAG is to transfer predetermined data sequences in series through IC components in a circuit board or in a part thereof and to sample the output data. As the topology and logical functions of the components of the circuit board to be tested are known in advance, an assumed output can also be determined. Test equipment may be used to compare the output data of a Device Under Test DUT with the assumed output and if they correspond with one another the device under test DUT operates correctly. If, in turn, the output data does not correspond with the assumed output, the circuit to be tested may be open, an outside signal may be connected thereto or a component in the circuit may be defective. In such a case, the defect can typically be determined by running different test data sequences through the device under test and by analysing the obtained output using software included in the test equipment.
The JTAG standard determines for both the test equipment comprising a JTAG controller and the device under test DUT an identical interface Test Access Port TAP, with a fixed synchronous line between them comprising at least five conductors for five compulsory signals: a Test ClocK signal TCK, a Test Mode Select signal TMS, Test Data Input TDI, Test Data Output TDO and a Ground reference signal GND. In addition according to the JTAG standard the line may be used for optionally conveying also a Test ReSeT signal TRST. The device under test DUT and the test equipment are placed close to one another so that they can be connected together with a cable comprising said at least five conductors and forming a synchronous line, and thereafter the testing of the device can be started.
A problem with the above arrangement is the testing of such devices to which test equipment is difficult or impossible to arrange with a fixed connection. This is emphasized, for example in space technology, where the chance to easily test circuit boards and to analyse defects is particularly important. For example, the defects that appear on a telecommunication satellite launched into the orbit must be analysed as quickly as possible. The satellites and other devices associated with space technology are typically kept as simple and light as possible, in which case a fixed installation of the test equipment to the devices is not to be desired. Consequently a need arises to test the circuit boards with the test equipment using remote control, without a fixed connection to the device under test.
What becomes a problem is then the synchronous line determined in accordance with the JTAG standard between the JTAG controller of the test equipment and the test access ports TAP of the device under test DUT. If the test equipment and device under test DUT are located far from one another, information between these two can typically only be transferred using an asynchronous and often wireless connection. Thus, the use of the test equipment according to the JTAG standard for testing circuit boards using remote control is impossible.
BRIEF DESCRIPTION OF THE INVENTION
It is an object of the invention to provide a system and an apparatus so as to solve the above problems. The objects of the invention are achieved with the system and apparatus, which are characterized in what is disclosed in the independent claims.
The preferred embodiments of the invention are disclosed in the dependent claims.
The invention is based on the fact that a fixed synchronous line restricting the JTAG standard-based testing can be avoided by employing transceivers both in test equipment and a device under test DUT. The transceivers arrange the signals arriving from a test access port TAP to be transferred through an asynchronous transmission path so that the received signals can again be synchronized into the mode required by the test access port TAP.
The system according to the invention provides significant advantages. The arrangement of the invention allows to carry out JTAG testing also in remote operation mode without a synchronous data transmission connection between the test equipment and the device under test. Existing IEEE1149.1 standard JTAG controllers and software thereof can be used in testing. A further advantage of the invention is that the structure of the transceivers allowing an asynchronous connection can be designed to be simple and economical, and the chances to employ JTAG testing can therefore be increased considerably. A still further advantage of a preferred embodiment of the invention is that an internal delay arrangement in the transceivers can be used to employ the test arrangement on different asynchronous connections, which may have different delays, in which case testing can also be carried out using connections which are slow in relation to a clock signal.


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“ILEE Standard Test Access Port and Boundary-Scan Architecture.” ILEE STD. 1149.1-1990 (Includes IEEE STD 1149.1A-1993), IEEE (1993) Entire Document.
“Supplemental to IEEE STD 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture” IEEE STD 1149.1-1994 Supply IEEE (1995) Entire Document.

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