JTAG test architecture for multi-chip pack

Details JTAG test architecture for multi-chip pack JTAG test architecture for multi-chip pack

2011-03-29

2011-03-29

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000

Reexamination Certificate

active

07917819

ABSTRACT:
A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.

REFERENCES:
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5491666 (1996-02-01), Sturges
patent: 5625631 (1997-04-01), Zimmerman et al.
patent: 5673276 (1997-09-01), Jarwala et al.
patent: 5862152 (1999-01-01), Handly et al.
patent: 5907562 (1999-05-01), Wrape et al.
patent: 6032278 (2000-02-01), Parvathala et al.
patent: 6094056 (2000-07-01), Bardsley et al.
patent: 6397361 (2002-05-01), Saitoh
patent: 6538469 (2003-03-01), Nguyen et al.
patent: 6546511 (2003-04-01), Sim et al.
patent: 2003/0079166 (2003-04-01), Vermeulen et al.
patent: 2379524 (2003-03-01), None
Hilla, S. “Boundary Scan Testing for Multichip Modules”, Proc. of the IEEE In'tl. Test Conf., pp. 224-231 (Sep. 1992).

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