Jtag test access port controller used to control...

Details Jtag test access port controller used to control... Jtag test access port controller used to control...

2005-02-01

2005-02-01

Decady, A. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06851079

ABSTRACT:
A circuit that may be used to implement boundary scan testing. The circuit generally comprises a pad circuit, a core logic, a cell, and a test circuit. The pad circuit may be configured to transfer a data signal in response to a pad control signal. The core logic may be configured to (i) exchange the data signal with the pad circuit and (ii) present a control signal. The cell may be configured to (i) transfer the data signal between the pad circuit and the core logic and (ii) swap the data signal and a test signal. The test circuit may-be configured to (i) exchange the test data signal with the cell, (ii) store a test control signal, and (iii) multiplex the test control signal and the control signal to present the pad control signal.

REFERENCES:
patent: 4335457 (1982-06-01), Early
patent: 5513186 (1996-04-01), Levitt
patent: 6125464 (2000-09-01), Jin
patent: 6418545 (2002-07-01), Adusumilli
patent: 6427216 (2002-07-01), El-Kik et al.
patent: 6446230 (2002-09-01), Chung
patent: 6536008 (2003-03-01), Nadeau-Dostie et al.
patent: 6587979 (2003-07-01), Kraus et al.

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