Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-13
2003-06-24
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S038110
Reexamination Certificate
active
06584590
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit testing. In particular, the invention relates to use of a Joint Test Action Group (JTAG) interface in integrated circuit testing.
2. Description of the Prior Art
The use of various functional components (blocks) and component libraries to create complex integrated circuits is becoming increasingly common. These complex integrated circuits are difficult to test. Traditionally, these integrated circuits incorporate a JTAG test port as a mechanism for emulating and debugging an integrated circuit under test. The JTAG test port is used to download debugging or other testing software from an external device, e.g., a JTAG debugger device, to the functional blocks located on the integrated circuit under test. The JTAG test port is also used to upload the test results from the functional blocks to the JTAG debugger device. A JTAG (test port) standard has been adopted by the Institute of Electrical and Electronics Engineers and is now defined as IEEE Standard 11491, IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated herein by reference. See also C. M. Mannales, and R. E. Tullos, “The Test Access Port and Boundary-Scan Architecture,” (IEEE Computer Society Prep, 1990) which is also incorporated herein by reference.
The JTAG test port provides control and observability of the functional blocks (test points) of the integrated circuits through scan access. Essentially, a large shift register referred to as a data chain is provided which allows data to be written to or read from desired test points inside the integrated circuit. These data chains are often controlled by a JTAG controller located external to the integrated circuit. The JTAG controller provides the necessary data and clock signals and an interface to a user or an application for automated testing of the functional blocks within an integrated circuit.
As shown in
FIG. 1
each of the functional blocks (core devices e.g. RAM
101
, ROM
103
, memory
105
) located on a typical integrated circuit
100
requires a particular JTAG test port (interface
107
for connecting to debugger devices
110
). Each JTAG test port may be a software or a hardware interface. In either case, it is designed specifically for testing the functions of the corresponding functional block. Furthermore, each of the JTAG test interfaces comprises a plurality of hardware pins (up to five hardware pins for each interface).
Each hardware pin takes up physical space on the integrated circuit and the circuit board where the integrated circuit is located. Thus, the cost associated with the manufacturing of integrated circuits and circuit boards increases with the increased number of hardware pins. Also, additional hardware pins increase the static on an integrated circuit
100
. This static causes interference in the functionality of the integrated circuit. Therefore, it is desired to minimize the number of hardware pins; however, current technology dictates that there must be a particular JTAG interface for each functional block located on an integrated circuit (under test). Each of these JTAG interfaces further requires a plurality of hardware pins.
One known solution for reducing the number of hardware pins is to utilize a common debugging platform that allows a plurality of functional blocks to share a common JTAG software or hardware interface. One such known debugging platform is Multi-ICE manufactured by Advanced RISC Machine, 985 University Avenue, Suite 5, Los Gatos Calif. 95030. The ARM Multi-ICE debugging platform can reduce the number of hardware pins, but the use of such a debugging platform limits the integrated circuit testing to the test software written specifically for the common debugging platform. This prevents using off-the-shelf JTAG debugger devices that a user may want or already have. It also creates the need for each vendor to develop different testing software in accordance with each particular debugging platform.
SUMMARY OF THE INVENTION
The present invention is directed to a JTAG port-sharing device that reduces the required number of hardware pins on an integrated circuit without limiting the integrated circuit testing to a particular debugging platform. The JTAG port-sharing device eliminates the need to have individual hardware pins for each functional block that requires a JTAG test interface and allows one set of hardware pins to be shared by a plurality of functional blocks. The JTAG port-sharing device is not limited by a particular debugging platform and allows the use of pre-owned and/or off-the-shelf testing software and/or JTAG debugger devices thereby leading to shorter development cycles and lower development costs.
In one embodiment, the present invention is a port-sharing device for testing an integrated circuit having a plurality of functional blocks, wherein the port-sharing device comprises (a) an on-chip interface port configured to be connected to a pin on the integrated circuit; and (b) at least two debugger ports, each configured to be connected to at least one debugger device to enable the at least one debugger device to test the plurality of functional blocks via the pin.
In another embodiment, the present invention is a method for testing an integrated circuit having a plurality of functional blocks, comprising the steps of (a) configuring an on-chip interface port of a port-sharing device to a pin on the integrated circuit; (b) configuring at least two debugger ports of the port-sharing device to be connected to at least one debugger device; and (c) testing the plurality of function blocks in the integrated circuit with the at least one debugger device via the port-sharing device and via the pin.
REFERENCES:
patent: 5812562 (1998-09-01), Baeg
patent: 5937154 (1999-08-01), Tegethoff
patent: 6026501 (2000-02-01), Hohl et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6035422 (2000-03-01), Hohl et al.
patent: 6430705 (2002-08-01), Wisor et al.
LandOfFree
JTAG port-sharing device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with JTAG port-sharing device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and JTAG port-sharing device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3144872