JTAG interface using existing I/O bus

Details JTAG interface using existing I/O bus JTAG interface using existing I/O bus

2005-10-21

2008-11-04

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

07447962

ABSTRACT:
A plurality of input circuits and a plurality of output circuits are connected to form a Boundary Scan Path Chain (BSPC). Part or all of the existing I/O bus is used as a test bus. When a test target system such as a logic circuit is tested, data of the input circuits is circulated in the BSPC to set the initial state. After a system clock is activated, data of the input circuits is loaded into shift registers provided in the input circuits or data of the output circuits is loaded into shift registers provided in the output circuits. A shift clock is activated to extract the data of the input or output circuits through the BSPC. Enable data is circulated in the BSPC, and data of the output circuits is supplied to the test bus only when the enable data is active.

REFERENCES:
patent: 5477545 (1995-12-01), Huang
patent: 5487074 (1996-01-01), Sullivan
patent: 6539536 (2003-03-01), Singh et al.
patent: 6988232 (2006-01-01), Ricchetti et al.
patent: 7159159 (2007-01-01), Sunter
patent: 2005/0204225 (2005-09-01), Whetsel
patent: 09-015300 (1997-01-01), None
patent: 11-326460 (1999-11-01), None

Affiliated with

Also associated with

Rating

JTAG interface using existing I/O bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with JTAG interface using existing I/O bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and JTAG interface using existing I/O bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4048416