Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-09-07
2009-08-18
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S734000
Reexamination Certificate
active
07577887
ABSTRACT:
A JTAG interface device capable of effectively debugging a mobile terminal by interfacing the mobile terminal with a JTAG emulator without an additional interface unit by allocating test pins of the JTAG emulator to some pins of a receptacle and then electrically connecting the test pins to the pins, and a method thereof. Accordingly, an operation for debugging the mobile terminal can be easily and effectively performed.
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IEEE Standard Test Access Port and Boundary-Scan Architecture, Jun. 14, 2001.
Lee Hong Degerman Kang & Waimey
LG Electronics Inc.
Merant Guerrier
Trimmings John P
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