Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-22
2004-10-12
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
06804802
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a method and/or architecture for instruction registers and decoders in programmable logic devices generally and, more particularly, to a method and/or architecture for a JTAG instruction register and decoder for programmable logic devices.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NORNOR logic.
Each macro-cell may contain a flip-flop called a macrocell flip-flop. The macrocell flip-flop is required to test the functionality of the macrocell and surrounding logic. Scan test procedures are conducted to test the macrocells and surrounding logic without increasing the device pin count. One such scan test procedure is a boundary scan test (i.e., JTAG boundary scan test in accordance with IEEE std 1149.1-1990, which is hereby incorporated by reference in its entirety). The PLD contains dedicated test logic to support the JTAG test procedures.
Referring to
FIG. 1
, a block diagram of a dedicated test logic circuit
2
illustrating a JTAG test access port (TAP) controller as contained in the IEEE standard is shown. A JTAG boundary scan test is conducted with JTAG test instrumentation connected to dedicated I/O pins of the PLD (i.e., a test access port or TAP). The TAP includes connections for a test clock (i.e., TCK), a test mode select (i.e., TMS), a test data input (i.e., TDI), and a test data output (i.e., TDO). A connection may also be provided for a test reset (i.e., TRST). The dedicated test logic includes a TAP controller
4
, an instruction register
6
, and test data registers
8
. The TAP controller
4
is a synchronous finite state machine that changes states in response to the signals TMS, TCK, and TRST. The TAP controller
4
controls the sequence of operations of the test logic circuitry in the PLD.
Operation of the TAP controller
4
is controlled by instructions received in the instruction register
6
. The instructions are decoded to determine operations and functions of the test data registers
8
.
Referring to
FIG. 2
, a block diagram illustrating a conventional dedicated test logic circuit
10
is shown. The circuit
10
has an instruction register
12
, an instruction decoder
14
, and a TAP controller
16
. The instruction decoder
14
is a combinatorial N:M decoder block, where N and M are integers. The instruction register
12
includes a shift register
18
and an update register
20
.
During a shift instruction register state of the TAP controller
16
, an N-bit instruction is serially shifted into the shift register
18
in response to a first clock signal (i.e., SHIFT_CLOCK). When the instruction is fully loaded, the TAP controller
18
moves to an update instruction register state. During the update instruction register state, the N-bit instruction is latched into the update register
20
on a falling edge of a second clock signal (i.e., UPDATE_CLOCK). Latching the N-bit instruction ensures that the test logic
10
is protected from transient data patterns that occur when another instruction is loaded into the instruction register
12
.
The latched N-bit instructions are presented to the instruction decoder
14
. The instruction decoder
14
operates asynchronously. The instruction decoder
14
decodes the N-bit instructions into M-bit instructions that control the operation and function of the test logic
10
. The instruction decoder
14
does not begin decoding an instruction until the instruction is loaded into the update register
20
during the update IR state of the TAP controller
18
.
Since the instruction decoder
14
is asynchronous, the design of the instruction decoder
14
requires special consideration to avoid generating anomalous instructions during instruction transitions. As a result, the design of the instruction decoder
14
is complicated. When instructions are added to the instruction set of the-TAP controller
16
, the design of the instruction decoder
14
must be re-evaluated to ensure that anomalous instructions are avoided. Functional simulation of the instruction decoder
14
may not catch glitches that can occur during instruction transitions. Furthermore, conventional instruction registers are generally asynchronous designs which are not preferred for synthesis.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a synchronous circuit configured to (i) shift a JTAG instruction signal, (ii) decode the JTAG instruction signal and (iii) load the decoded JTAG instruction signal into a register.
The objects, features and advantages of the present invention include providing an instruction register and decoder circuit that may (i) be used easily with synthesis tools, (ii) allow the addition of instructions with minimal redesign, (iii) ensure proper instruction generation during instruction transitions without additional circuitry, (iv) provide a synchronous design, (v) decode instructions before updating and/or (vi) minimize anomalous instructions during transitions.
REFERENCES:
patent: 5325368 (1994-06-01), James et al.
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5377198 (1994-12-01), Simpson et al.
patent: 5428624 (1995-06-01), Blair et al.
patent: 5636227 (1997-06-01), Segars
patent: 5689516 (1997-11-01), Mack et al.
patent: 5781560 (1998-07-01), Kawano et al.
patent: 6058255 (2000-05-01), Jordan
“IEEE Std 1149.1-1990: IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE, 1990.*
“IEEE Std 1149.1b-1994: Supplement to IEEE Std 1149.1-1990”, IEEE, 1994.
Lulla Navaz
Nayak Anup
Lamarre Guy J.
Maiorana P.C. Christopher P.
Miller Robert M.
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