Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-05
2004-07-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06766486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to integrated circuits, and in particular, to a JTAG tester for use with integrated circuits.
2. Background Information
A group of key electronic companies proposed a technique whereby integrated circuits (i.e., chips) on a printed circuit board could be tested easily by incorporating software-controlled hardware into the integrated circuit during manufacturing. This technique was approved by the well-known Institute of Electrical and Electronics Engineers (IEEE) as IEEE Standard 1149.1. Because the group of key electronic companies was known as the Joint Test Action Group, the terms “IEEE Standard 1149.1” and “JTAG Standard” often are used interchangeably.
The IEEE 1149.1 or JTAG Standard specifies the hardware and software needed to enable testing of chips. According to the JTAG Standard, a single cell of a shift-register is designed into the integrated circuit logic and linked to every digital pin of the integrated circuit. This single cell links the JTAG circuitry to the integrated circuit's internal core logic. A group of cells on a particular integrated circuit is referred to as a register. The register logic becomes active when performing JTAG testing and remains passive under normal integrated circuit operation.
Also according to the JTAG Standard, the integrated circuit architecture for each JTAG compatible device has a test access port (TAP port), which has four (or optionally five) pins, any one of which may be referred to as a “boundary pin” or a “test access pin.” For example, a test clock (TCK) pin receives a test clock signal for the device under test. A test mode select (TMS) pin accepts commands to select particular test modes. A test data in (TDI) pin accepts data into the device under test. A test data output (TDO) pin sends data out from the device under test.
There are several testers currently available. Many are expensive multiport JTAG testers or high pin count functional testers. A 9000 series tester from Schlumberger is an example. There are other less expensive single port JTAG testers. These testers connect the JTAG ports in series in a chain and test the JTAG ports in parallel. This scheme is slow and susceptible to failure if any of the devices in the chain malfunction.
This is because JTAG was originally designed to devices mounted on a printed circuit board by serially connecting TAP ports to each other. When testing, data is scanned in through one TAP port to the next TAP port until all TAP ports are all filled. A command is run and data is shifted out in the same manner. This scheme is adequate for testing an assembly of printed circuit boards because if a particular printed circuit board is bad, it does not matter where on the printed circuit board the fault is located. The entire printed circuit fails and can be rejected.
When testing integrated circuits using JTAG, multiple integrated circuits are placed in a test tray. The test tray has sockets for a certain number of devices. If one or more of the sockets in the test tray fails to function, because the device in the socket is faulty, for example, then none of the integrated circuits in any of the sockets in the tray can be tested properly. To properly test all of the integrated circuits, the test must be performed multiple times, which multiplies the retest rate significantly. This is problematic because as the number of tests needed is increased, the time it takes to test a tray of devices is increased and the efficiency of the test process is reduced.
Moreover, the traditional scheme does not allow testing of trays whose sockets are not fully populated with devices. This means that no partial trays can be tested using the conventional testing scheme.
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Blakley Sokoloff Taylor & Zafman LLP
Chaudry Mujtaba
De'cady Albert
Intel Corporation
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