Jitter suppressing delay locked loop circuits and related...

Details Jitter suppressing delay locked loop circuits and related... Jitter suppressing delay locked loop circuits and related...

2007-05-01

2007-05-01

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S161000

Reexamination Certificate

active

10925522

ABSTRACT:
Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.

REFERENCES:
patent: 4809209 (1989-02-01), White
patent: 5554945 (1996-09-01), Lee et al.
patent: 5717619 (1998-02-01), Spurbeck et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6677793 (2004-01-01), Chan et al.
patent: 6794912 (2004-09-01), Hirata et al.
patent: 6854002 (2005-02-01), Conway et al.
patent: 2005/0052211 (2005-03-01), Jung et al.

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