Jitter resistant clock regenerator

Details Jitter resistant clock regenerator Jitter resistant clock regenerator

1998-05-04

2001-04-17

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S362000

Reexamination Certificate

active

06219396

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a jitter resistant clock regenerator advantegeously applicable to terminal equipment, and more particularly to a jitter resistant clock regenerator for restoring from transmitted data received on a channel a program clock signal which is used for processing program data that are defined in this specification generally as various data for use in media in an upper layer.
2. Description of the Background Art
Today, there is an increasing demand for a network system integrating multiple types of media, and its related techniques have been intensively developed. Such a network is adapted to transmit over the same channel various types of medium data, called program data hereinbelow, to be processed at different processing rates which is independent of the transmission rate of the channel.
For these program data to preferably be processed at their appropriate processing rates on a receiver site, some mechanism is required for transmitting together with the program data clock signals, called program clock signals from now on, corresponding to the processing rates of the program data, and for restoring them at the receiver site.
Thus, a method is employed which embeds timing signals in the program data at the transmitter site so that the receiver site can restore the program clock signals by extracting the timing signals from the received program data. Such a method conventionally uses a PLL (Phase-Locked Loop) circuit to align the phase of oscillation with the phase of the timing signals, thus to restore the program clock signals needed for processing the program data.
It is unavoidable, however, that jitter is involved in the transmitted data owing to transmission delay or the like encountered on the channel. Therefore, extracting the timing signals for the program data directly from the transmitted data on which the jitter is involved, and supplying the extracted timing signals to the PLL circuit may cause degradation in the accuracy of the restored program clock signals due to the timing signals momentarily fluctuated.
In view of this, it would be possible to design the lowpass filter constituting the PLL circuit so as to have its time constant increased to reduce the effect of the jitter. This, however, presents another problem of complicating the circuit and delaying the start time of the clock signal acquisition.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a jitter resistant clock regenerator capable of restoring a program clock signal free from jitter with a simple circuit configuration without including a PLL circuit.
To accomplish the object, in accordance with the present invention, a clock regenerator for restoring a clock signal of program data from transmitted data synchronized with a transmission clock signal on a transmission channel, wherein the program data are for use in various types of media in an upper layer, and the clock signal of the program data is independent of the transmission clock signal, comprises: a receiving buffer for temporarily storing the transmitted data received over the transmission channel; a read clock selector circuit for monitoring a data amount of the transmitted data stored in the receiving buffer, and for selecting one of read clock signals in response to the data amount; and a program clock acquisition circuit for reading out the transmitted data from the receiving buffer in response to a read clock signal selected by the read clock selecting circuit, and for restoring the clock signal of the program data from the transmitted data.
The clock regenerator in accordance with the present invention selects a lower rate read clock signal when the amount of data stored in the receiving buffer is less than a reference level, and a higher rate read clock signal when the data amount is greater than the reference level so that the data amount is kept substantially at an average value. As a result, the average rate with respect to the rate of the program clock signal to be detected, which has a much longer period than that of the fluctuations in the timing signals due to the jitter, takes a constant rate free from the effect of the jitter. This enables the program clock signal unaffected by the jitter to be recovered by a simpler circuit without using a PLL circuit.


REFERENCES:
patent: 4054747 (1977-10-01), Pachynski, Jr.
patent: 4181975 (1980-01-01), Jenkins
patent: 4596026 (1986-06-01), Cease et al.
patent: 5014271 (1991-05-01), Fujimoto
patent: 5210773 (1993-05-01), Schmid et al.

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