Jitter injection circuit, pattern generator, test apparatus,...

Details Jitter injection circuit, pattern generator, test apparatus,... Jitter injection circuit, pattern generator, test apparatus,...

2011-03-08

2011-03-08

Beausoliel, Robert (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07904776

ABSTRACT:
Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.

REFERENCES:
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patent: 6256003 (2001-07-01), Tsuchiya et al.
patent: 7221202 (2007-05-01), Yayla
patent: 2004/0131089 (2004-07-01), Uemura et al.
patent: 2005/0044463 (2005-02-01), Frisch
patent: WO2007-049365 (2007-05-01), None

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