JFET transistor manufacturing method

Details JFET transistor manufacturing method JFET transistor manufacturing method

1999-03-30

2000-11-28

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438197, 438199, 438188, 438189, 257369, 257133, 257134, 257272, H01L 218238

Patent

active

061534536

ABSTRACT:
The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.

REFERENCES:
patent: 5296409 (1994-03-01), Merrill et al.
patent: 5605851 (1997-02-01), Palmieri
French Search Report from French Patent Application 98/04208, filed Mar. 31, 1998.
Patent Abstracts of Japan, vol. 018, No. 105 (E-1512), Feb. 21, 1994 & JP-A-05 304258 (Toshiba Corp,).

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