Iterative decoder employing multiple external code error...

Details Iterative decoder employing multiple external code error... Iterative decoder employing multiple external code error...

2007-12-18

2007-12-18

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S792000

Reexamination Certificate

active

10892738

ABSTRACT:
Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

REFERENCES:
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patent: 6484283 (2002-11-01), Stephen et al.
patent: 6570919 (2003-05-01), Lee
patent: 6606724 (2003-08-01), Krieger et al.
patent: 2 332 835 (1999-06-01), None

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