Isotropic etching of a hemispherical grain silicon layer to impr

Details Isotropic etching of a hemispherical grain silicon layer to impr Isotropic etching of a hemispherical grain silicon layer to impr

1999-09-03

2000-04-04

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438396, 438398, 438964, H01L 218242

Patent

active

060460849

ABSTRACT:
A process for creating a storage node structure, for a DRAM capacitor structure, featuring increased storage node surface area, via use of an HSG silicon layer, on an underlying storage node shape, has been developed. The process features the use of an isotropic, buffered HF etch procedure, applied to the HSG silicon layer, to increase the space between the concave and convex features, of the HSG silicon layer. The increased space between the concave and convex features of the HSG silicon layer, allows a capacitor dielectric layer, of uniform thickness, to be formed on the isotopically etched, HSG silicon layer.

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patent: 5837582 (1998-11-01), Su
patent: 5913119 (1999-06-01), Lin et al.
patent: 5930625 (1999-07-01), Lin et al.

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