Isotropic assisted dual trench etch

Details Isotropic assisted dual trench etch Isotropic assisted dual trench etch

1997-12-18

2001-01-30

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S704000

Reexamination Certificate

active

06180466

ABSTRACT:

TECHNICAL FIELD
The present invention relates to manufacturing semiconductor devices with trench isolation and, more particularly, to manufacturing ultra large scale integration and high density semiconductor devices with submicron design features and active regions isolated by shallow insulated trenches.
BACKGROUND ART
Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor technology for isolating active regions.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The active region typically includes source/drain regions of a transistor formed in the semiconductor substrate or epitaxial layer, spaced apart by a channel region. A gate electrode for switching the transistor is formed on the channel with a gate oxide layer therebetween. The quality and thickness of the gate oxide are crucial to performance and device reliability.
The electrical isolation of active regions is typically accomplished by defining field regions bounding the active regions, defined by a source/drain mask applied to a barrier nitride layer deposited over the semiconductor substrate, typically doped monocrystalline silicon or an epitaxial layer formed thereon. An isolating field oxide regions is typically formed by thermal oxidation of semiconductor substrate.
One type of isolation is known as Local Oxidation Of Silicon (LOCOS), in which the entirety of the field oxide is formed by heating the substrate with the field regions exposed to an oxidizing gas, such as oxygen or water vapor. LOCOS methodology, however, disadvantageously results in the formation of a field oxide region having tapering edges, because the oxidizing species for forming the field oxide diffuses horizontally after penetrating the substrate. This tapering end portion resembles and, therefore, is commonly referred to as, a “bird's beak.”
LOCOS methodology is thus subject to several inherent problems. For example, while the horizontal extent of the bird's beak can be loosely controlled by the stress induced in the masking layers adjacent to the field, this same stress can cause strain defects in the active areas including point defects, dislocations, stacking faults, as well as catastrophic failures such as delamination, particle generation, etc. Moreover, aggressive scaling of gate electrode dimension into the deep submicron regime, such as less than about 0.25 microns, requires tighter source/drain region to source/drain region spacing, which is adversely affected by the bird's beak attendant upon LOCOS methodology.
Another type of isolation is known as shallow trench isolation (STI). This form of isolation is typically accomplished by etching a trench in the substrate, conducting a thermal oxidation step to grow an oxide liner on the trench walls to control the silicon-silicon dioxide interface quality, and filling the lined trench with an insulating material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP), to complete the trench isolation structure. A typical trench isolation structure thus comprises an internal surface with side surfaces extending into the substrate (or epitaxial layer) with edges at the main surface of the substrate and at the bottom of the trench.
A difficulty with trench isolation is that the sharp top corners of the trench, e.g. from about 90° to about 110°, induce stress, which is transmitted to the active regions of the substrate, resulting in degradation of the quality of the gate oxide and, hence, adversely affecting device performance and reliability. A conventional approach to this problem involves growing the oxide liner at a high enough (dry) oxidation temperature, e.g. about 950° C. and above typically at 1100° C., to cause the top corners of the trench to become rounded, thereby reducing the induced stress.
As feature sizes, e.g. isolation trenches, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to define reliable trench isolation structures. For example, the side-walls of the trench tend to expand inwardly and vertically align during edge-rounding oxidation. This condition, termed “reentrance,” disadvantageously induces stress at the side-walls of the trench, which is transmitted to the active regions. With smaller feature sizes, especially in the deep submicron regime such as 0.18 microns, reentrance is exacerbated since greater aspect ratios result in greater vertical alignment of the side-walls during edge-rounding oxidation.
In addition, conducting edge-rounding oxidation at about 950° C. is costly in terms of time, e.g. a period of about two to three hours, undesirably reducing production throughput. A conventional approach for improving production throughput involves raising the temperature of the edge-rounding oxidation, typically to about 1,100° C., wherein sufficient edge rounding may take place in about twenty minutes. Edge-rounding oxidation at such high temperatures, however, causes other difficulties such as “slip” of the trench surface, which is the dislocation of crystal planes exposed when the trench opening is etched. Slip is a major factor of stress transmitted to the active regions, causing degradation of the gate oxide quality over the active regions, thereby adversely affecting device performance.
Attempts to enhance production throughput by other conventional means as, for example, by employing water vapor as the oxidizing species (wet oxidation) instead of molecular oxygen (dry oxidation), have generally been found to greatly aggravate the stress problems due to reentrance and slip.
DISCLOSURE OF THE INVENTION
There exists a continuing need for a shallow trench isolation methodology wherein the resulting gate oxide layer at the trench edges exhibits high reliability. There is a need for reducing the stress induced at the corners and side walls of the isolation trenches, especially for deep submicron geometries.
A need also exists for improving the throughput in rounding the top edges of the isolation trench without inducing additional stresses due to, e.g. , reentrance and slip.
These and other needs are met by the present invention, in which the top corners of the isolation trench are anisotropically etched before performing the edge-rounding oxidation to produce a liner oxide with rounded corners. Consequently, the edge-rounding liner oxidation step can be performed at significantly lower temperatures, e.g. about 800° C. to 900° C., avoiding the additional stresses induced by conventional methods. Furthermore, the lower temperatures enable the use of wet oxidation without the attendant disadvantages of reentrance and slip.
Accordingly, one aspect of the invention is method of manufacturing a semiconductor device having an active region isolated by an insulated trench, comprising: forming a pad oxide on a main surface of a semiconductor substrate or an epitaxial layer formed on a semiconductor substrate; forming a nitride layer on the pad oxide layer; etching to remove selected portions of the nitride layer and to form an opening therein having side surfaces; removing portions of the pad oxide layer beneath the opening in the nitride layer; isotropically etching: to remove portions of the semiconductor substrate or the epitaxial layer beneath the opening in the nitride layer; and to undercut the pad oxide beneath the nitride layer, thereby exposing a portion of the substrate or the epitaxial layer beneath the nitride layer; anisotropically etching to remove portions of the semiconductor substrate or the epitaxial layer to form a trench opening having an

Affiliated with

Also associated with

Rating

Isotropic assisted dual trench etch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isotropic assisted dual trench etch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isotropic assisted dual trench etch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2524966