Isolation testing circuit and testing circuit optimization...

Details Isolation testing circuit and testing circuit optimization... Isolation testing circuit and testing circuit optimization...

2006-12-05

2006-12-05

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C716S030000, C716S030000

Reexamination Certificate

active

07146550

ABSTRACT:
In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors731to736for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers721to726for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks701to706incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal709and test input transit signals710to714, which are connected in a single stroke of a pen, can be reduced shortest.

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