Isolation structure for a memory cell using Al 2 O 3...

Details Isolation structure for a memory cell using Al 2 O 3... Isolation structure for a memory cell using Al 2 O 3...

2007-10-16

2007-10-16

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S424000, C438S425000

Reexamination Certificate

active

10873226

ABSTRACT:
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region.

REFERENCES:
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4015281 (1977-03-01), Nagata et al.
patent: 4035829 (1977-07-01), Ipri et al.
patent: 5463236 (1995-10-01), Sakao
patent: 5677231 (1997-10-01), Maniar et al.
patent: 5869376 (1999-02-01), Tomioka
patent: 5903026 (1999-05-01), Gonzalez et al.
patent: 5982005 (1999-11-01), Hidaka et al.
patent: 6504214 (2003-01-01), Yu et al.
patent: 6657276 (2003-12-01), Karlsson et al.
patent: 6759699 (2004-07-01), Chi
patent: 6902971 (2005-06-01), Grudowski
patent: 2002/0135048 (2002-09-01), Ahn et al.
patent: 2002/0197823 (2002-12-01), Yoo et al.
patent: 2004/0077151 (2004-04-01), Bhattacharyya
patent: 2004/0092054 (2004-05-01), Mouli et al.
“Electrically Enhanced Trench Isolation for ULSI Applications” IBM Technical Disclosure Bulletin, IBM Corp., vol. 32, No. 12, May 1, 1990, pp. 400-402, XP000105413 ISSN: 0018-8689; figures; New York, US.
“Inversion-Free Trench Isolation” IBM Technical Disclosure Bulletin, IBM Corp., vol. 33, No. 3B, Aug. 1, 1990, pp. 332-333, XP000124373 ISSN: 0018-8689; figures; New York, US.
“Amorphus (CeO2)0.67(A12O3)0.33high-k gate dielectric thin films on silicon,” L. Yan, et al., published May 28, 2003.
“Effect of Polysilicon Gate on the Flatband Voltage Shift and Mobility Degradation for ALD-A12O3Gate Dielectric,” J. H. Lee et al., © 2000 IEEE.
“80 nm poly-silicon gated n-FETs with ultra-thin A12O3gate dielectric for ULSI applications,” D.A. Buchanan et al., © 2000 IEEE.
“Si-Doped Aluminates for High Temperature Metal-Gate CMOS: Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications,” L. Manchanda, et al., Bell Laboratories, Lucent Technologies, Murray Hill, N.J. 07974, © 2000, IEEE.
Preliminary Report on Patentability and Written Report of the International Searching Authority, Jun. 23, 2004.

Affiliated with

Also associated with

Rating

Isolation structure for a memory cell using Al 2 O 3... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation structure for a memory cell using Al 2 O 3..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation structure for a memory cell using Al 2 O 3... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3845923