Isolation structure configurations for modifying stresses in...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...

Reexamination Certificate

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C257S369000, C257S374000, C257S499000, C257S401000, C257S506000

Reexamination Certificate

active

06876053

ABSTRACT:
An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

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patent: 6455912 (2002-09-01), Kim et al.
Hamada et al., “A New Aspect of Mechanical Stress Effects in Scaled MOS Devices,” IEEE Transactions on Electron Devices, vol. 38, No. 4, Apr. 1991, pp. 895-900.

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