Isolation scheme to prevent field oxide edge from oxide loss

Details Isolation scheme to prevent field oxide edge from oxide loss Isolation scheme to prevent field oxide edge from oxide loss

1998-05-20

2000-05-02

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438297, 438298, 438262, H01L 21336, H01L 21265

Patent

active

060571977

ABSTRACT:
A semiconductor integrated circuit such as a flash memory device with a novel isolation structure. Field isolation (130) is defined on a substrate (10). A spacer (107) is formed at the edges of the field isolation to protect the field isolation from oxide loss during subsequent processing steps, such as HF dips to remove polysilicon or polymer stringers that are often a part of a flash EEPROM process, for example.

REFERENCES:
patent: 5576230 (1996-11-01), Guldi
patent: 5717086 (1998-02-01), Kim et al.
patent: 5756390 (1998-05-01), Juengling et al.
patent: 5763309 (1998-06-01), Chang
patent: 5793089 (1998-08-01), Fulford et al.

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