Isolation scheme for static and dynamic FPGA partial...

Details Isolation scheme for static and dynamic FPGA partial... Isolation scheme for static and dynamic FPGA partial...

2008-01-30

2009-06-16

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

C326S040000, C326S047000

Reexamination Certificate

active

07548095

ABSTRACT:
An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-wells are respectively disposed in the first and second deep n-wells. First and second segments of Flash memory are disposed in the in first and second p-wells. N-type regions are disposed in each deep n-well between the outer boundary of the p-wells and the outer boundary of the deep n-wells.

REFERENCES:
patent: 2008/0175060 (2008-07-01), Liu et al.
patent: 2008/0283896 (2008-11-01), Noguchi et al.

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