Isolation of memory cells in cross point arrays

Details Isolation of memory cells in cross point arrays Isolation of memory cells in cross point arrays

2001-10-25

2003-10-21

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000, C257S295000

Reexamination Certificate

active

06636436

ABSTRACT:

TECHNICAL FIELD
The technical field is memory cells for cross point memory arrays. More specifically, the technical field is memory cells having an isolation feature built into the memory cells.
BACKGROUND
Cross point memory arrays include horizontal word lines that cross vertical bit lines. Memory cells are located at the cross points of the word and bit lines, and function as the storage elements of a memory array. The memory cells each store a binary state of either “1” or “0.” Memory devices typically include one time programmable (OTP) or re-programmable memory cells. A re-programmable memory cell can be switched among binary states. An OTP memory cell's state is permanent once the cell is programmed. Re-programmable memory cells are desirable because they can be reprogrammed after sale and can be used in random access memory devices.
One type of re-programmable memory device is magnetic random access memory (MRAM).
FIG. 1
illustrates a conventional MRAM memory array
10
having resistive memory cells
12
located at cross points of word lines
14
and bit lines
16
. The word lines
14
extend horizontally along rows of the memory array
10
, and the bit lines
16
extend vertically along columns of the memory array
10
.
FIG. 2
illustrates a conventional MRAM memory cell
12
. The memory cell
12
may be a spin dependent tunneling (“SDT”) device. The memory cell
12
includes a pinned ferro-magnetic layer
24
and a free ferro-magnetic layer
18
. The pinned layer
24
has a magnetization that has a fixed orientation, illustrated by the arrow
26
. The magnetization of the free layer
18
, illustrated by the bidirectional arrow
28
, can be oriented in either of two directions along an “easy axis” of the free layer
18
. If the magnetizations of the free layer
18
and the pinned layer
24
are in the same direction, the orientation of the memory cell
12
is “parallel.” If the magnetizations are in opposite directions, the orientation is “anti-parallel.” The two orientations correspond to the binary states of “1” and “0,” respectively.
The free layer
18
and the pinned layer
24
are separated by an insulating tunnel barrier layer
20
. The insulating tunnel barrier layer
20
allows quantum mechanical tunneling to occur between the free layer
18
and the pinned layer
24
. The tunneling is electron spin dependent, making the resistance of the memory cell
12
a function of the relative orientations of the magnetizations of the free layer
18
and the pinned layer
24
. The resistance of the memory cell
12
may have a “low” value of R if the orientation is parallel, and a “high” value of R+&Dgr;R if the orientation is anti-parallel.
Each memory cell
12
in the memory array
10
can have its binary state changed by a write operation. Write currents supplied to the word line
14
and the bit line
16
crossing at a specific memory cell
12
switch the magnetization of the free layer
18
between parallel and anti-parallel with respect to the pinned layer
24
. A current Iy passing through the bit line
16
results in the magnetic field Hx. A similar magnetic field Hy is created when a current Ix passes through the word line
14
. The magnetic fields Hx and Hy combine to switch the magnetic orientation of the memory cell
12
. The change in resistance due to the changing memory cell magnetization is readable to determine the binary state of the memory cell
12
.
As illustrated in
FIG. 1
, a cross point memory array may have all memory cells connected together as one large parallel circuit. Ideally, current passes only through a selected memory cell during a read operation. However, in a large parallel circuit memory array, currents flow through unselected memory elements during read operations. These currents are referred to as “sneak path currents.” If the cross point memory array has a high density of memory cells, neighboring memory cells must be isolated from one another so that a selected memory cell is not affected by sneak path currents during a read operation.
Conventional parallel-connected cross point arrays often include a control device in series with each memory cell to prevent sneak path currents. One conventional control device is a series MOS transistor located in a memory cell. The series MOS transistor is controlled by an additional conductor run in parallel with the word line. The series MOS transistor isolates the selected memory cell from unselected memory cells in the memory array by breaking parallel connections of memory cells. During read operations, only the MOS transistor in the selected memory cell is turned on. The MOS transistors in unselected cells are turned off, thereby preventing sneak path currents from flowing through unselected memory cells.
A disadvantage to MOS transistors is that they consume valuable substrate area, and the memory cells must be larger in order to accommodate electrical contacts from the memory cell to the substrate. In addition, MOS transistors require a control gate and a complex physical structure for implementation in a thin film memory system.
Another way to prevent sneak path currents is to place a diode in series with each memory element in an array. The series diode may be a single crystal diode located in the substrate, or a thin film diode located in the plane with the memory elements. The series diode isolates the memory cells, but the associated diode forward voltage drops can be large in conventional devices. Large forward voltage drops are undesirable because they negatively affect the ability to read and write data in the memory cells. In addition, leakage currents are relatively high in conventional diode devices, which also negatively affects the ability to read and write data.
A need therefore exists for a memory array having an isolation capability that does not occupy substrate area, and that does not negatively affect the ability to read or write to the memory array.
SUMMARY
According to a first aspect, a memory array includes memory cells located at cross points of first and second conductors. The memory cells include an isolation element in series with a re-writeable storage element. The storage element stores a binary state of the memory cell, and the isolation element isolates the memory cell in the memory array. The isolation elements include a pillar structure with an N+ region surrounding a P− region, and a gate oxide disposed at an end of the pillar. Each isolation element functions as a transistor, where the transistor can disconnect the tunnel junction from sidewalls of the pillar, preventing current flow through the memory cell.
According to the first aspect, the isolation elements provide an isolation feature to the memory cells that does not occupy space in the substrate. This allows more memory cells to be placed on the substrate, increasing array density.
In addition, the memory cells have a low forward voltage drop. Low forward voltage drops enhance the ability to sense the binary states of the memory cells, improving the ability to read the memory array. The isolation elements also allow low leakage currents.
According to a second aspect, the memory array can be manufactured using low temperature processes.
According to the second aspect, a multi-plane memory array can be formed from stacked memory arrays. The multi-plane memory array is a high density memory device.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying figures.


REFERENCES:
patent: 5659499 (1997-08-01), Chen et al.
patent: 5940319 (1999-08-01), Durlam et al.
patent: 6351408 (2002-02-01), Schwarzl et al.
patent: 6538297 (2003-03-01), Odagawa et al.
patent: 6555858 (2003-04-01), Jones et al.
patent: 1109169 (2001-06-01), None

Affiliated with

Also associated with

Rating

Isolation of memory cells in cross point arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation of memory cells in cross point arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation of memory cells in cross point arrays will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3115490